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High-Level Design Tools for Floating Point FPGAs

Published: 22 February 2015 Publication History

Abstract

This tutorial describes tools for efficiently implementing floating point applications on FPGAs. We present both the SDK for OpenCL and DSP Builder Advanced Blockset and show that they can be effectively used to implement many floating point applications. The methods for optimizing application performance are also described.
In this tutorial we focus on a few applications, including Fast Fourier transform, matrix multiplication, finite impulse response filter and a Cholesky decomposition. In all cases we show what the tools are capable of achieving, and more importantly how a user can take advantage of the various floating-point centric features that are made available. We also discuss how these tools can automatically use FPGA architectural features such as hardened floating-point DSP available on Altera Arria 10 family.

References

[1]
Altera Corporation, Altera SDK for OpenCL, http://www.altera.com/products/software/opencl
[2]
Altera Corporation, Altera DSP Builder Advanced Blockset, http://www.altera.com/technology/dsp/advanced-blockset
[3]
IEEE standard for binary floating-point arithmetic. ANSI/IEEE Std. 754-1985, pages 1--58, 2008.
[4]
Khronos OpenCL Working Group. The OpenCL Specification, version 1.1.48, June 2009.
[5]
M. Garrido, J. Grajal, M. Sanchez, and O. Gustafsson. "Pipelined radix-2k feedforward FFT architectures", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 21(1):23--32, 2013.
[6]
E. Swartzlander and H. Saleh, "FFT implementation with fused floating-point operations", IEEE Transactions on Computers, 61(2):284--288, 2012.
[7]
M. Langhammer, "Floating Point Datapath Synthesis for FPGAs", International Conference on Field Programmable Logic and Applications, pp. 355--360, 2008.
[8]
B. Pasca, and M. Langhammer, "Floating Point DSP Block Architecture for FPGAs", ACM/SIGDA International Symposium on FPGAs, Monterey California, Feb, 2015.
[9]
de Dinechin, F.; Joldes, M.; Pasca, B., "Automatic generation of polynomial-based hardware architectures for function evaluation," Application-specific Systems Architectures and Processors (ASAP), 21st IEEE International Conference on, pp. 216--222, 7-9 July 20.

Cited By

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  • (2018)Hardware Implementation of Floating-Point ArithmeticHandbook of Floating-Point Arithmetic10.1007/978-3-319-76526-6_8(267-320)Online publication date: 3-May-2018
  • (2017)From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272062325:10(2867-2880)Online publication date: 1-Oct-2017

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  1. High-Level Design Tools for Floating Point FPGAs

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    cover image ACM Conferences
    FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
    February 2015
    292 pages
    ISBN:9781450333153
    DOI:10.1145/2684746
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 22 February 2015

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    Author Tags

    1. floating point
    2. fpgas
    3. optimization

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    Cited By

    View all
    • (2018)Hardware Implementation of Floating-Point ArithmeticHandbook of Floating-Point Arithmetic10.1007/978-3-319-76526-6_8(267-320)Online publication date: 3-May-2018
    • (2017)From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272062325:10(2867-2880)Online publication date: 1-Oct-2017

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