ABSTRACT
Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.
- A. Pelkonen, K. Masselos, and M. Cupk, "System-level modeling of dynamically reconfigurable hardware with systemc," in 10th Reconfigurable Architectures Workshop, 2003. Google ScholarDigital Library
- N. Alachiotis and A. Stamatakis, "Efficient floating-point logarithm unit for fpgas," in Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on, April 2010, pp. 1--8.Google Scholar
- B. Lee and K. Lever, "Logarithmic number system and floating-point implementations of a well-conditioned rls estimation algorithm on fpga," in Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on, vol. 1, Nov 2003, pp. 109--113 Vol.1.Google Scholar
- B. Lee and N. Burgess, "Some results on taylor-series function approximation on fpga," in Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on, vol. 2, Nov 2003, pp. 2198--2202 Vol.2.Google Scholar
- R. Lundgreen, D. Thompson, D. Arnold, D. Long, and G. Miner, "Initial results of a low-cost sar: Yinsar," in Geoscience and Remote Sensing Symposium, 2000. Proceedings. IGARSS 2000. IEEE 2000 International, vol. 7, 2000, pp. 3045--3047 vol.7.Google Scholar
Index Terms
- Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)
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