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Silicon Verification using High-Level Design Tools (Abstract Only)

Published: 22 February 2015 Publication History

Abstract

Modern FPGAs comprise ever more complex blocks to enable a wide variety of customer applications. Verification of the complex blocks can be a time consuming process, especially at the late stages of the release cycle. A key challenge is the time it takes to create circuits that can run on a target device to test a given block. This paper demonstrates how High-Level Design tools, such as Altera SDK for OpenCL, can be utilized to aid in this work to verify the operation of complex hardened blocks. As a proof of concept, we present the methodology used to verify the correctness of hardened single-precision floating point adder, subtractor and multiplier units on Altera Arria 10 FPGA in a single day. Each design comprised an instance of a hardened floating point unit, either an adder, subtractor or a multiplier, and a functional equivalent there of implemented purely using Lookup Tables (LUTs). Both the hardened module instance and the LUT implementation were generated from OpenCL description using Altera SDK for OpenCL. The results for each computation were compared between the two implementations and any single discrepancy constituted a test failure. To simplify the test, the I/O for each design comprised LEDs (for pass/fail/running/done status) and two switches -- start and reset.
The test design for adder, subtractor and a multiplier were all written in OpenCL, the compilation of each design took approximately 30 minutes for each test design. Each design tested 4 billion test vectors, generated on-chip using a Mersenne Twister, and each test completed within 30 seconds. All tests passed verification in hardware.

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  • (2015)Floating-Point DSP Block Architecture for FPGAsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689071(117-125)Online publication date: 22-Feb-2015

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  1. Silicon Verification using High-Level Design Tools (Abstract Only)

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    cover image ACM Conferences
    FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
    February 2015
    292 pages
    ISBN:9781450333153
    DOI:10.1145/2684746
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Publication History

    Published: 22 February 2015

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    Author Tags

    1. dsp blocks
    2. floating point
    3. fpga

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    FPGA '15 Paper Acceptance Rate 20 of 102 submissions, 20%;
    Overall Acceptance Rate 125 of 627 submissions, 20%

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    • (2015)Floating-Point DSP Block Architecture for FPGAsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689071(117-125)Online publication date: 22-Feb-2015

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