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SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

Published: 14 March 2015 Publication History

Abstract

Phase Change Memory (PCM) has better scalability and smaller cell size comparing to DRAM. However, further scaling PCM cell in deep sub-micron regime results in significant thermal based write disturbance (WD). Naively allocating large inter-cell space increases cell size from 4F2 ideal to 12F2. While a recent work mitigates WD along word-lines through disturbance resilient data encoding, it is ineffective for WD along bit-lines, which is more severe due to widely adopted $\mu$Trench structure in constructing PCM cell arrays. Without mitigating WD along bit-lines, a PCM cell still has 8F2, which is 100% larger than the ideal. In this paper, we propose SD-PCM for achieving reliable write operations in super dense PCM. In particular, we focus on mitigating WD along bit-lines such that we can construct super dense PCM chips with 4F2 cell size, i.e., the minimal for diode-switch based PCM. Based on simple verification-n-correction (VnC), we propose LazyCorrection and PreRead to effectively reduce VnC overhead and minimize cascading verification during write. We further propose (n:m)-Alloc for achieving good tradeoff between VnC overhead minimization and memory capacity loss. Our experimental results show that, comparing to a WD-free low density PCM, SD-PCM achieves 80% capacity improvement in cell arrays while incurring around 0-10% performance degradation when using different (n:m) allocators.

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  1. SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

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    cover image ACM Conferences
    ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems
    March 2015
    720 pages
    ISBN:9781450328357
    DOI:10.1145/2694344
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    Published: 14 March 2015

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    Author Tags

    1. phase change memory
    2. write disturbance

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    ASPLOS '15 Paper Acceptance Rate 48 of 287 submissions, 17%;
    Overall Acceptance Rate 535 of 2,713 submissions, 20%

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    Cited By

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    • (2024)FSDedup: Feature-Aware and Selective Deduplication for Improving Performance of Encrypted Non-Volatile Main MemoryACM Transactions on Storage10.1145/366273620:4(1-33)Online publication date: 1-May-2024
    • (2024)A Scalable Wear Leveling Technique for Phase Change MemoryACM Transactions on Storage10.1145/363114620:1(1-26)Online publication date: 30-Jan-2024
    • (2024)Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence DomainACM Transactions on Embedded Computing Systems10.1145/360747323:6(1-34)Online publication date: 11-Sep-2024
    • (2024)Mitigating Write Disturbance in Non-Volatile Memory via Coupling Machine Learning with Out-of-Place Updates2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00092(1184-1198)Online publication date: 2-Mar-2024
    • (2023)An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change MemoryIEEE Transactions on Computers10.1109/TC.2022.319707172:4(1150-1162)Online publication date: 1-Apr-2023
    • (2023)ESD: An ECC-assisted and Selective Deduplication for Encrypted Non-Volatile Main Memory2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071011(977-990)Online publication date: Mar-2023
    • (2022)ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306870441:4(950-963)Online publication date: Apr-2022
    • (2022)CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCMIEEE Transactions on Computers10.1109/TC.2021.306857771:5(992-1007)Online publication date: 1-May-2022
    • (2022)WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change MemoryIEEE Access10.1109/ACCESS.2022.314598610(11420-11431)Online publication date: 2022
    • (2021)CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile MemoriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301592540:7(1340-1353)Online publication date: Jul-2021
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