research-article

A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization

Authors:

Alaeddin A. AydinerAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 12, Issue 3

Article No.: 25, Pages 1 - 20

https://doi.org/10.1145/2700246

Published: 21 September 2015 Publication History

Abstract

Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early stage when the design database is not complete, including extraction, modeling, and optimization. This article tackles these fundamental issues of early-stage power grid design from architecture to layout. The proposed methods have been silicon validated on 32nm on-market chips and successfully applied to a 22nm design for its early-stage power grid design. The findings from such practices reveal that, for sub-32nm chips, an intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and needs to be well addressed at early stage.

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Cited By

Dong XSun SChen ZYang JZhuo C(2023)Agile Full-Chip Sign-Off in the Post-Moore Era2023 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC58779.2023.10219241(1-5)Online publication date: 26-Jun-2023
https://doi.org/10.1109/CSTIC58779.2023.10219241
Zhuo CLuo SGan HHu JShi Z(2020)Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291784439:7(1498-1510)Online publication date: 17-Jun-2020
https://dl.acm.org/doi/10.1109/TCAD.2019.2917844
Li YZhuo CZhou P(2019)A Cross-Layer Framework for Temporal Power and Supply Noise PredictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287182038:10(1914-1927)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2871820
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Index Terms

A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Model verification and validation

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 12, Issue 3

Special Issue on Cross-Layer System Design and Regular Papers

September 2015

207 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2828988

Editor:
Krishnendu Chakrabarty
Duke University, USA

Issue’s Table of Contents

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 21 September 2015

Accepted: 01 September 2014

Revised: 01 September 2014

Received: 01 June 2014

Published in JETC Volume 12, Issue 3

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Cited By

Dong XSun SChen ZYang JZhuo C(2023)Agile Full-Chip Sign-Off in the Post-Moore Era2023 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC58779.2023.10219241(1-5)Online publication date: 26-Jun-2023
https://doi.org/10.1109/CSTIC58779.2023.10219241
Zhuo CLuo SGan HHu JShi Z(2020)Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291784439:7(1498-1510)Online publication date: 17-Jun-2020
https://dl.acm.org/doi/10.1109/TCAD.2019.2917844
Li YZhuo CZhou P(2019)A Cross-Layer Framework for Temporal Power and Supply Noise PredictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287182038:10(1914-1927)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2871820
Zhuo CUnda KShi YShih W(2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2834438
Liu SChen BZhuo C(2019)Revisiting EAVP for Power Delivery Decoupling Optimization2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)10.1109/EMCCompo.2019.8919705(129-131)Online publication date: Oct-2019
https://doi.org/10.1109/EMCCompo.2019.8919705
Luo SZhuo CGan H(2018)Noise-aware DVFS transition sequence optimization for battery-powered IoT devicesProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196080(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196080
Luo SZhuo CGan H(2018)Noise-Aware DVFS Transition Sequence Optimization for Battery-Powered IoT Devices2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)10.1109/DAC.2018.8465802(1-6)Online publication date: Jun-2018
https://doi.org/10.1109/DAC.2018.8465802

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