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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

Published: 03 August 2015 Publication History

Abstract

Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy.
We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 12, Issue 1
    July 2015
    210 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/2810396
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Publication History

    Published: 03 August 2015
    Accepted: 01 January 2015
    Revised: 01 December 2014
    Received: 01 October 2014
    Published in JETC Volume 12, Issue 1

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    Author Tags

    1. Access-Transistor-Free
    2. Adaptive Write Scheme
    3. Leakage-Current Filtering
    4. Low-Power
    5. March Algorithm
    6. Memory Testing
    7. Memristive Crossbar
    8. Memristor
    9. Online Resistance Monitoring
    10. ReRAM
    11. Variation-Aware Design

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    • the Air Force Office of Scientific Research under the MURI

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    • (2020)Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write schemeAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01576-xOnline publication date: 1-Jan-2020
    • (2019)A System-Level Simulator for RRAM-Based Neuromorphic Computing ChipsACM Transactions on Architecture and Code Optimization10.1145/329105415:4(1-24)Online publication date: 8-Jan-2019
    • (2018)A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable FunctionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275973126:1(73-81)Online publication date: Jan-2018
    • (2018)Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memoriesAEU - International Journal of Electronics and Communications10.1016/j.aeue.2018.07.02394(392-406)Online publication date: Sep-2018
    • (2017)Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature RangesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263408325:4(1224-1235)Online publication date: 1-Apr-2017
    • (2017)More Efficient Testing of Metal-Oxide Memristor–Based MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.260886336:6(1018-1029)Online publication date: 1-Jun-2017
    • (2016)In-place Repair for Resistive Memories Utilizing Complementary Resistive SwitchesProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934590(350-355)Online publication date: 8-Aug-2016
    • (2016)A low-power hybrid reconfigurable architecture for resistive random-access memories2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446057(102-113)Online publication date: Mar-2016
    • (2015)Toward large-scale access-transistor-free memristive crossbarsThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059067(563-568)Online publication date: Jan-2015

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