Jody Maick Matos
Augusto Neutzling
André Reis
ABSTRACT
This paper presents an improved benchmark suite to jointly consider logic synthesis and physical design. Usually, benchmark circuits were provided by the physical design and the logic synthesis communities separately, according to their specific needs. The files provided for each benchmark set were restricted to the views necessary for the community. Additional specifications of design intents are necessary to express optimization goals that can be shared by logic synthesis and physical design communities, as circuits alone do not carry sufficient information to establish a benchmark with a clear optimization goal. In this paper, we describe benchmarks as a set composed of circuits, design intents (constraints), floorplan, target library and technology. Disregarding pieces of information provided for the benchmarks can change the associated criticality and affect the combined or isolated outcome of logic synthesis and physical design. The proposition of this benchmark suite brings attention to the problem of considering adequately the complete context of design intent throughout the flow.
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Index Terms
- A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design
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