short-paper

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits

Authors:

William Patterson,

Alexander ZaslavskyAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 45 - 50

https://doi.org/10.1145/2742060.2742066

Published: 20 May 2015 Publication History

Abstract

Noise analysis in nonlinear logic circuits requires models that take into account time-varying biasing conditions. When considering thermal noise, which moves the circuit away from its equilibrium point, a correct modeling approach has to go beyond the additive white Gaussian noise (AWGN) used in classical noise analysis. Even when accurate models are available, running standard Monte-Carlo simulations that will expose rare soft errors may still be computationally prohibitive. Probabilistic methods are often preferred for estimating the failure rate. However, these approaches may not provide any insight about the dynamic response to noise events. In this paper, we target both problems in the sub-threshold logic application domain. We first provide a time-domain model for fundamental, technology-independent thermal noise in sub-threshold circuits. Then, we use this model to generate noise input files for SPICE transient analysis. The effectiveness of the approach is demonstrated using 7nm FinFET predictive technology models (PTM) for an inverter and a NAND gate.

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Cited By

Donato MBahar RPatterson WZaslavsky A(2018)A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271770537:3(643-656)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2717705
Han XDonato MBahar RZaslavsky APatterson WCoskun AMargala MBehjat LHan J(2016)Design of Error-Resilient Logic Gates with Reinforcement Using ImplicationsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902983(191-196)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902983
Donato MBahar RPatterson WZaslavsky A(2016)A fast simulator for the analysis of sub-threshold thermal noise transientsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897960(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897960

Index Terms

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 20 May 2015

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GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Donato MBahar RPatterson WZaslavsky A(2018)A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271770537:3(643-656)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2717705
Han XDonato MBahar RZaslavsky APatterson WCoskun AMargala MBehjat LHan J(2016)Design of Error-Resilient Logic Gates with Reinforcement Using ImplicationsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902983(191-196)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902983
Donato MBahar RPatterson WZaslavsky A(2016)A fast simulator for the analysis of sub-threshold thermal noise transientsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897960(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897960

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