skip to main content
10.1145/2742060.2742078acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
short-paper

Reinforcement Learning for Thermal-aware Many-core Task Allocation

Published:20 May 2015Publication History

ABSTRACT

To maintain reliable operation, task allocation for many-core processors must consider the heat interaction of processor cores and network-on-chip routers in performing task assignment. Our approach employs reinforcement learning, machine learning algorithm that performs task allocation based on current core and router temperatures and a prediction of which assignment will minimize maximum temperature in the future. The algorithm updates prediction models after each allocation based on feedback regarding the accuracy of previous predictions. Our new algorithm is verified via detailed many-core simulation which includes on-chip routing. Our results show that the proposed technique is fast (scheduling performed in <1 ms) and can efficiently reduce peak temperature by up to 8°C in a 49-core processor (4.3°C on average) versus a competing task allocation approach for a series of SPLASH-2 benchmarks.

References

  1. A. K. Coskun, T. S. Rosing, and K. Whisnant, "Temperature aware task scheduling in MPSoCs," in Proc. DATE, Mar. 2007, pp. 1659--1664. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. C. H. Yu, C.-L. Lung, Y.-L. Ho, R.-S. Hsu, D.-M. Kwai, and S.-C. Chang, "Thermal-aware on-line scheduler for 3-D many-core processor throughput optimization," IEEE TCAD, vol. 33, no. 5, May 2014.Google ScholarGoogle Scholar
  3. A. Coskun, T. Rosing, K. Whisnant, and K. Gross, "Static and dynamic temperature-aware scheduling for multiprocessor SoCs," IEEE TVLSI, vol. 16, no. 9, pp. 1127--1140, Sep. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. I. Yeo and E. J. Kim, "Temperature-aware scheduler based on thermal behavior grouping in multicore systems," in Proc. DATE, May 2009, pp. 946--951. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. V. Hanumaiah, S. Vrudhula, and K. Chatha, "Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors," IEEE TCAD, vol. 30, no. 11, pp. 1677--1690, Nov. 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. W. Hung et al., "Thermal-aware IP virtualization and placement for networks-on-chip architecture," in Proc ICCD, Oct. 2004, pp. 430--437. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Z. Qian and C.-Y. Tsui, "A thermal-aware application specific routing algorithm for network-on-chip design," in Proc. ASP-DAC, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Y. Ge and Q. Qiu, "Dynamic thermal management for multimedia applications using machine learning," in Proc. DAC, June 2011, pp. 95--100. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. T. Ebi, D. Kramer, W. Karl, and J. Henkel, "Economic learning for thermal-aware power budgeting in many-core architectures," in Proc. CODES+ISSS, Oct 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. G.-Y. Pan, J.-Y. Jou, and B.-C. Lai, "Scalable power management using multilevel reinforcement learning for multiprocessors," ACM Trans. Des. Autom. Electron. Syst., vol. 19, no. 4, pp. 33:1--33:23, Aug. 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. H. Chen and etc., "Spatially-aware optimization of energy consumption in consolidated data center systems," in ASME 2011 Pac. Rim Tech. Conf. and Exhibition on Packaging and Integration of Elec. and Phot. Sys.Google ScholarGoogle Scholar
  12. A. G. Barto, Reinforcement learning: An introduction. MIT press, 1998.Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. E. Rotem et al., "Power management architecture of the 2nd generation Intel core microarchitecture, formerly codenamed Sandy Bridge," in Hot Chips, August 2011.Google ScholarGoogle Scholar
  14. L. Baird and A. W. Moore, "Gradient descent for general reinforcement learning," Adv. in Neural Information Proc. Sys., pp. 968--974, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. L. Sheng et al., "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in Proc. IEEE/ACM Micro, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. C. Sun et al., "DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling," in Proc. IEEE/ACM Int'l Symp. on NoC, 2012, pp. 201--210. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. T. E. Carlson, W. Heirman, and L. Eeckhout, "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulations," in Int'l Conf. for High Perf. Comput., Network., Stor. and Analysis, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Reinforcement Learning for Thermal-aware Many-core Task Allocation

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
      May 2015
      418 pages
      ISBN:9781450334747
      DOI:10.1145/2742060

      Copyright © 2015 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 20 May 2015

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • short-paper

      Acceptance Rates

      GLSVLSI '15 Paper Acceptance Rate41of148submissions,28%Overall Acceptance Rate312of1,156submissions,27%

      Upcoming Conference

      GLSVLSI '24
      Great Lakes Symposium on VLSI 2024
      June 12 - 14, 2024
      Clearwater , FL , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader