research-article

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Authors:

Dimitrios Stamoulis,

Dimitrios Rodopoulos,

Brett H. Meyer,

Dimitrios Soudris,

Francky Catthoor,

Zeljko ZilicAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 57 - 62

https://doi.org/10.1145/2742060.2742079

Published: 20 May 2015 Publication History

Abstract

In this paper, we propose EDA methodologies for efficient, datapath-wide reliability analysis under Bias Temperature Instability (BTI). The proposed EDA flow combines the efficiency of atomistic, pseudo-transient BTI modeling with the accuracy of commercial Static Timing Analysis (STA) tools. In order to reduce the transistor inventory that needs to be tracked by the STA solver, we develop a threshold-pruning methodology to identify the variation-critical part of a design. That way, we accelerate variation-aware STA iterations, with a maximum speedup of 6.82x achieved for representative benchmark circuits. We substantiate the efficiency of the proposed framework for realistic designs. For a CPU datapath, our threshold-pruning technique outperforms built-in pruning commands of the STA solver by 16.87% in terms of runtime improvement. We demonstrate the impact of BTI after three years of operation, with clock frequency degradation up to 24% and functional yield reduction below 90% for higher frequencies.

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Cited By

Stamoulis DCai EJuan DMarculescu D(2018)HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8341973(19-24)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8341973
Chen ZStamoulis DMarculescu D(2018)ProfitIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277282237:10(2064-2075)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2772822
Corbetta SWeckx PRodopoulos DStamoulis DCatthoor F(2018)Time-Efficient Modeling and Simulation of True Workload Dependency for BTI-Induced Degradation in Processor-Level Platform SpecificationsHarnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms10.1007/978-3-319-91962-1_10(217-235)Online publication date: 24-Oct-2018
https://doi.org/10.1007/978-3-319-91962-1_10
Show More Cited By

Index Terms

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 20 May 2015

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European Union - HARPA project
Greek State Scholarship Foundation (IKY)

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GLSVLSI '15

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GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

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Cited By

Stamoulis DCai EJuan DMarculescu D(2018)HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8341973(19-24)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8341973
Chen ZStamoulis DMarculescu D(2018)ProfitIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277282237:10(2064-2075)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2772822
Corbetta SWeckx PRodopoulos DStamoulis DCatthoor F(2018)Time-Efficient Modeling and Simulation of True Workload Dependency for BTI-Induced Degradation in Processor-Level Platform SpecificationsHarnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms10.1007/978-3-319-91962-1_10(217-235)Online publication date: 24-Oct-2018
https://doi.org/10.1007/978-3-319-91962-1_10
Cai EStamoulis DMarculescu D(2016)Exploring aging deceleration in FinFET-based multi-core systems2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/2966986.2967039(1-8)Online publication date: 7-Nov-2016
https://dl.acm.org/doi/10.1145/2966986.2967039
Stamoulis DCorbetta SRodopoulos DWeckx PDebacker PMeyer BKaczer BRaghavan PSoudris DCatthoor FZilic ZCoskun AMargala MBehjat LHan J(2016)Capturing True Workload Dependency of BTI-induced Degradation in CPU ComponentsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902992(373-376)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902992
Stamoulis DTsoumanis KRodopoulos DMeyer BPekmestzi KSoudris DZilic Z(2016)Efficient variability analysis of arithmetic units using linear regression techniquesAnalog Integrated Circuits and Signal Processing10.1007/s10470-016-0712-687:2(249-261)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1007/s10470-016-0712-6

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