short-paper

Speed Binning Using Machine Learning And On-chip Slack Sensors

Authors:

Mark Tehranipoor,

LeRoy WinembergAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 155 - 160

https://doi.org/10.1145/2742060.2742080

Published: 20 May 2015 Publication History

Abstract

Speed binning of integrated circuits using Fmax test of a SoC requires application of complex functional and structural test patterns. Today's test-pattern-based speed binning techniques incur high test cost in terms of long test time and requires significant effort to generate effective patterns. In this paper we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmax values from a set of randomly tested die during wafer sort. The proposed flow has been demonstrated in a SoC circuit at 28/32nm technology. The worst-case miss-binning of the predictor is within 6% of the nominal Fmax.

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Cited By

Zhang DRen QSu D(2022)On-Chip Structures for Fmax Binning and OptimizationSensors10.3390/s2204138222:4(1382)Online publication date: 11-Feb-2022
https://doi.org/10.3390/s22041382
Su MLin WKuo YLi CFang EHsueh S(2021)Chip Performance Prediction Using Machine Learning Techniques2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT52063.2021.9427338(1-4)Online publication date: 19-Apr-2021
https://doi.org/10.1109/VLSI-DAT52063.2021.9427338
Zhang DWang XRahman MTehranipoor M(2018)An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC PiraciesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2850807(1-14)Online publication date: 2018
https://doi.org/10.1109/TVLSI.2018.2850807
Show More Cited By

Index Terms

Speed Binning Using Machine Learning And On-chip Slack Sensors
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 20 May 2015

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GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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June 30 - July 2, 2025

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Cited By

Zhang DRen QSu D(2022)On-Chip Structures for Fmax Binning and OptimizationSensors10.3390/s2204138222:4(1382)Online publication date: 11-Feb-2022
https://doi.org/10.3390/s22041382
Su MLin WKuo YLi CFang EHsueh S(2021)Chip Performance Prediction Using Machine Learning Techniques2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT52063.2021.9427338(1-4)Online publication date: 19-Apr-2021
https://doi.org/10.1109/VLSI-DAT52063.2021.9427338
Zhang DWang XRahman MTehranipoor M(2018)An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC PiraciesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2850807(1-14)Online publication date: 2018
https://doi.org/10.1109/TVLSI.2018.2850807
Sadi MKannan SWinemberg LTehranipoor M(2017)SoC Speed Binning Using Machine Learning and On-Chip Slack SensorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.260280636:5(842-854)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2602806
Sadi MContreras GTran DChen JWinemberg LTehranipoor M(2016)BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning2016 IEEE International Test Conference (ITC)10.1109/TEST.2016.7805862(1-10)Online publication date: Nov-2016
https://doi.org/10.1109/TEST.2016.7805862

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