skip to main content
10.1145/2742060.2742093acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
research-article

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

Published: 20 May 2015 Publication History

Abstract

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independent-gate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is established by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of both shorted-gate and independent-gate standard cells are then characterized according to lambda-based layout design rules for FinFET devices. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independent-gate FinFETs.

References

[1]
M. Pedram and S. Nazarian, "Thermal modeling, analysis, and management in vlsi circuits: Principles and methods," Proceedings of the IEEE, vol. 94, no. 8, pp. 1487--1501, 2006.
[2]
R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, "Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits," Proceedings of the IEEE, vol. 98, no. 2, pp. 253--266, 2010.
[3]
D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J. M. Rabaey, "Ultralow-power design in near-threshold region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237--252, 2010.
[4]
L. Chang, Y.-k. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, "Extremely scaled silicon nano-cmos devices," Proceedings of the IEEE, vol. 91, no. 11, pp. 1860--1873, 2003.
[5]
S. Chaudhuri and N. K. Jha, "Finfet logic circuit optimization with different finfet styles: Lower power possible at higher supply voltage," in VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, 2014, pp. 476--482.
[6]
T. Sairam, W. Zhao, and Y. Cao, "Optimizing finfet technology for high-speed and low-power design," in Proceedings of the 17th ACM Great Lakes symposium on VLSI. ACM, 2007, pp. 73--77.
[7]
C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, "A comparative study of advanced mosfet concepts," Electron Devices, IEEE Transactions on, vol. 43, no. 10, pp. 1742--1753, 1996.
[8]
L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, "Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body mosfets," in INTERNATIONAL ELECTRON DEVICES MEETING. IEEE; 1998, 2001, pp. 99--102.
[9]
A. R. Brown, A. Asenov, and J. R. Watling, "Intrinsic fluctuations in sub 10-nm double-gate mosfets introduced by discreteness of charge and matter," Nanotechnology, IEEE Transactions on, vol. 1, no. 4, pp. 195--200, 2002.
[10]
A. Muttreja, N. Agarwal, and N. K. Jha, "Cmos logic design with independent-gate finfets," in Computer Design, 2007. ICCD 2007. 25th International Conference on. IEEE, 2007, pp. 560--567.
[11]
F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, and G. Groeseneken, "Understanding the basic advantages of bulk finfets for sub-and near-threshold logic circuits from device measurements," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, no. 7, pp. 439--442, 2012.
[12]
T. Cakici, K. Kim, and K. Roy, "Finfet based sram design for low standby power applications," in Quality Electronic Design, 2007. ISQED'07. 8th International Symposium on. IEEE, 2007, pp. 127--132.
[13]
J. Ouyang and Y. Xie, "Power optimization for finfet-based circuits using genetic algorithms," in SOC Conference, 2008 IEEE International. IEEE, 2008, pp. 211--214.
[14]
S. K. Gupta, W.-S. Cho, A. A. Goud, K. Yogendra, and K. Roy, "Design space exploration of finfets in sub-10nm technologies for energy-efficient near-threshold circuits," in Device Research Conference (DRC), 2013 71st Annual. IEEE, 2013, pp. 117--118.
[15]
T. Cui, Y. Wang, X. Lin, S. Nazarian, and M. Pedram, "Semi-analytical current source modeling of finfet devices operating in near/sub-threshold regime with independent gate control and considering process variation." in ASP-DAC, 2014, pp. 167--172.
[16]
T. Cui, S. Chen, Y. Wang, S. Nazarian, and M. Pedram, "An efficient semi-analytical current source model for finfet devices in near/sub-threshold regime considering multiple input switching and stack effect," in Quality Electronic Design (ISQED), 2014 15th International Symposium on. IEEE, 2014, pp. 575--581.
[17]
N. K. Jha and D. Chen, Nanoelectronic Circuit Design. springer, 2010.
[18]
X. Lin, Y. Wang, and M. Pedram, "Joint sizing and adaptive independent gate control for finfet circuits operating in multiple voltage regimes using the logical effort method," in Proceedings of the International Conference on Computer-Aided Design. IEEE Press, 2013, pp. 444--449.
[19]
M. Alioto, "Analysis of layout density in finfet standard cells and impact of fin technology," in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on. IEEE, 2010, pp. 3204--3207.
[20]
A. A. Goud, S. K. Gupta, S. H. Choday, and K. Roy, "Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length si finfets," in Device Research Conference (DRC), 2013 71st Annual. IEEE, 2013, pp. 51--52.
[21]
M. Alioto, "Comparative evaluation of layout density in 3t, 4t, and mt finfet standard cells," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no. 5, pp. 751--762, 2011.
[22]
Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale cmos spacer finfet for the terabit era," Electron Device Letters, IEEE, vol. 23, no. 1, pp. 25--27, 2002.
[23]
D. M. Fried, "The design, fabrication and characterization of independent-gate finfets," Ph.D. dissertation, Cornell Unive, 2004.
[24]
U. Gogineni, J. A. Del Alamo, and C. Putnam, "Rf power potential of 45 nm cmos technology," in Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on. IEEE, 2010, pp. 204--207.
[25]
G. G. Shahidi, "Evolution of cmos technology at 32 nm and beyond," in Custom Integrated Circuits Conference, 2007. CICC'07. IEEE. IEEE, 2007, pp. 413--416.

Cited By

View all
  • (2018)An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage RegimesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.26401856:2(172-183)Online publication date: 1-Apr-2018
  • (2017)TEI-powerACM Transactions on Design Automation of Electronic Systems10.1145/301994122:3(1-25)Online publication date: 21-Apr-2017
  • (2017)Transistor Count Optimization in IG FinFET Network DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.262945136:9(1483-1496)Online publication date: Sep-2017
  • Show More Cited By

Index Terms

  1. Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
    May 2015
    418 pages
    ISBN:9781450334747
    DOI:10.1145/2742060
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    In-Cooperation

    • IEEE CEDA
    • IEEE CASS

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 20 May 2015

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. finfet
    2. independent gate control
    3. layout
    4. power density

    Qualifiers

    • Research-article

    Funding Sources

    • Defense Advanced Research Projects Agency

    Conference

    GLSVLSI '15
    Sponsor:
    GLSVLSI '15: Great Lakes Symposium on VLSI 2015
    May 20 - 22, 2015
    Pennsylvania, Pittsburgh, USA

    Acceptance Rates

    GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)24
    • Downloads (Last 6 weeks)3
    Reflects downloads up to 28 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2018)An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage RegimesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.26401856:2(172-183)Online publication date: 1-Apr-2018
    • (2017)TEI-powerACM Transactions on Design Automation of Electronic Systems10.1145/301994122:3(1-25)Online publication date: 21-Apr-2017
    • (2017)Transistor Count Optimization in IG FinFET Network DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.262945136:9(1483-1496)Online publication date: Sep-2017
    • (2016)Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors2016 29th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2016.7905480(253-258)Online publication date: Sep-2016

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media