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Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

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Published:20 May 2015Publication History

ABSTRACT

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independent-gate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is established by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of both shorted-gate and independent-gate standard cells are then characterized according to lambda-based layout design rules for FinFET devices. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independent-gate FinFETs.

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  1. Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

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    • Published in

      cover image ACM Conferences
      GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
      May 2015
      418 pages
      ISBN:9781450334747
      DOI:10.1145/2742060

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      Publication History

      • Published: 20 May 2015

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      GLSVLSI '15 Paper Acceptance Rate41of148submissions,28%Overall Acceptance Rate312of1,156submissions,27%

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