research-article

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

Authors:

Shahin Nazarian,

Massoud PedramAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 33 - 38

https://doi.org/10.1145/2742060.2742093

Published: 20 May 2015 Publication History

Abstract

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independent-gate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is established by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of both shorted-gate and independent-gate standard cells are then characterized according to lambda-based layout design rules for FinFET devices. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independent-gate FinFETs.

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Cited By

Cui TLi JWang YNazarian SPedram M(2018)An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage RegimesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.26401856:2(172-183)Online publication date: 1-Apr-2018
https://doi.org/10.1109/TETC.2016.2640185
Lee WHan KWang YCui TNazarian SPedram M(2017)TEI-powerACM Transactions on Design Automation of Electronic Systems10.1145/301994122:3(1-25)Online publication date: 21-Apr-2017
https://dl.acm.org/doi/10.1145/3019941
Possani VReis ARibas RMarques Fda Rosa L(2017)Transistor Count Optimization in IG FinFET Network DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.262945136:9(1483-1496)Online publication date: Sep-2017
https://doi.org/10.1109/TCAD.2016.2629451
Show More Cited By

Index Terms

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells
1. Hardware
  1. Hardware validation

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 20 May 2015

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GLSVLSI '15

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GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Cui TLi JWang YNazarian SPedram M(2018)An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage RegimesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.26401856:2(172-183)Online publication date: 1-Apr-2018
https://doi.org/10.1109/TETC.2016.2640185
Lee WHan KWang YCui TNazarian SPedram M(2017)TEI-powerACM Transactions on Design Automation of Electronic Systems10.1145/301994122:3(1-25)Online publication date: 21-Apr-2017
https://dl.acm.org/doi/10.1145/3019941
Possani VReis ARibas RMarques Fda Rosa L(2017)Transistor Count Optimization in IG FinFET Network DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.262945136:9(1483-1496)Online publication date: Sep-2017
https://doi.org/10.1109/TCAD.2016.2629451
Wang LCui TNazarian SWang YPedram M(2016)Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors2016 29th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2016.7905480(253-258)Online publication date: Sep-2016
https://doi.org/10.1109/SOCC.2016.7905480

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