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Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors

Published: 20 May 2015 Publication History

Abstract

This work presents a framework which detects online and at operand level of granularity all the vectors which excite a set of diagnosed failures in combinational modules. The failures may be of various types and may change over time. We propose to utilize this ability to detect failures at operand level of granularity to improve yield, by not discarding those chips containing failing and redundant computational units as long as they are not failing at the same time. The main challenge in realization of such a framework is the ability for on-chip storage of all the (test) vectors which excite the set of diagnosed failures. A major contribution of this work is to significantly minimize the number of stored test cubes by inserting only a few but carefully-selected "false alarm" vectors. As a result, a computational unit may be mis-diagnosed as failing for a given operand however we show such cases are rare and the chip may continue to be used.

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  1. Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors

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    cover image ACM Conferences
    GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
    May 2015
    418 pages
    ISBN:9781450334747
    DOI:10.1145/2742060
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 20 May 2015

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