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Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

Published: 20 May 2015 Publication History

Abstract

With aggressive technology scaling in nanometer regime, a significant fraction of dynamic power is consumed in the clock network due to its high switching activity. Clock networks are typically synthesized and routed to optimize for zero clock skew. However, clock skew optimization is often accompanied with routing overhead which increases the clock net capacitance thereby consuming more power. In this paper, we propose a skew bounded buffer tree resynthesis algorithm to optimize clock net capacitance after the clock network has been synthesized and routed. Our algorithm restricts the skew of the designs within a specified margin from its original skew, and does not introduce any additional Design Rule Check (DRC) violation. Experimental results on industrial designs, with clock networks synthesized and routed by an industrial tool, have demonstrated that our approach can achieve an average reduction of 5.6% and 3.5% in clock net capacitance and clock dynamic power respectively with a marginal overhead in the clock skew.

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Cited By

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  • (2017)A Clock Tree Optimization Framework with Predictable Timing QualityProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062184(1-6)Online publication date: 18-Jun-2017
  • (2016)Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario CompressionACM Transactions on Design Automation of Electronic Systems10.1145/288360921:4(1-27)Online publication date: 18-May-2016

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  1. Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

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    cover image ACM Conferences
    GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
    May 2015
    418 pages
    ISBN:9781450334747
    DOI:10.1145/2742060
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 20 May 2015

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    Author Tags

    1. clock tree
    2. dynamic power
    3. post-cts optimization

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    GLSVLSI '15: Great Lakes Symposium on VLSI 2015
    May 20 - 22, 2015
    Pennsylvania, Pittsburgh, USA

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    GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2017)A Clock Tree Optimization Framework with Predictable Timing QualityProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062184(1-6)Online publication date: 18-Jun-2017
    • (2016)Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario CompressionACM Transactions on Design Automation of Electronic Systems10.1145/288360921:4(1-27)Online publication date: 18-May-2016

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