Subramanyam Sripada
ABSTRACT
With shrinking technologies and increasing design complexities, it is common to have a large number of modes (functional, scan, test and so on) and corners (PVT device and interconnect). This leads to an explosion in the number of scenarios (#modes × #corners) that need to be validated for timing. While multiple tactics are required to handle this problem, one essential way to address this is by reducing the number of modes by merging individual modes into superset modes. However, with the overriding necessity to maintain sign-off accuracy, mode merging with high merge-factor is very complex. In this paper, we propose a novel automated timing graph based approach to mode merging that is designed to meet these requirements. By construction, there is an inbuilt validation that the merged constraints correctly model the intent of original constraints. This technology is tested on large industrial designs and the results are provided.
- Jing-Jia Nian; Shih-Heng Tsai; Shao-Lun Huang, "A unified Multi-Corner Multi-Mode static timing analysis engine," ASP-DAC, 2010 Google Scholar
Digital Library
- Onaissi, S.; Taraporevala, F.; Jinfeng Liu; Najm, F., "A fast approach for static timing analysis covering all PVT corners," DAC, 2011 Google ScholarDigital Library
- Rajagopal, K. A.; Sivakumar, R.; Arvind, N. V.; Sreeram, C.; Visvanathan, V.; Dhuri, S.; Chander, R.; Fortner, P.; Sripada, S.; Qiuyang Wu, "A comprehensive solution for true hierarchical timing and crosstalk delay signoff," VLSI Design, 2006. Google ScholarDigital Library
- Subrangshu K. Das; Ajay J. Daga; Aishwarya Singh; Vikas Sachdeva, "The Automatic Generation of Merged-Mode Design Constraints", DAC, 2009 User TrackGoogle Scholar
- Shuo Zhou; Bo Yao; Hongyu Chen; Yi Zhu; Chung-Kuan Cheng; Hutton, M.; Collins, T.; Srinivasan, S.; Chou, N.; Suaris, P., "Improving the efficiency of static timing analysis with false paths," ICCAD-2005. Google ScholarDigital Library
- "Using the Synopsys Design Constraints Format", Application Note, Version 2.0, 2013, Synopsys Inc.Google Scholar
Index Terms
- A timing graph based approach to mode merging
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