skip to main content
10.1145/2744769.2744807acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

CMOST: a system-level FPGA compilation framework

Published: 07 June 2015 Publication History

Abstract

Programming difficulty is a key challenge to the adoption of FPGAs as a general high-performance computing platform. In this paper we present CMOST, an open-source automated compilation flow that maps C-code to FPGAs for acceleration. CMOST establishes a unified framework for the integration of various system-level optimizations and for different hardware platforms. We also present several novel techniques on integrating optimizations in CMOST, including task-level dependence analysis, block-based data streaming, and automated SDF generation. Experimental results show that automatically generated FPGA accelerators can achieve over 8x speedup and 120x energy gain on average compared to the multi-core CPU results from similar input C programs. CMOST results are comparable to those obtained after extensive manual source-code transformations followed by high-level synthesis.

References

[1]
J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang, "High-level synthesis for FPGA: From prototyping to deployment," IEEE Trans. on CAD, vol. 30, no. 4, 2011.
[2]
H. K. So and R. Brodersen, "A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH," ACM TECS. Jan. 2008, pp. 28.
[3]
E. S. Chung, J. C. Hoe, and K. Mai, "CoRAM: an in-fabric memory architecture for FPGA-based computing," the 19th ACM/SIGDA intl. symp. FPGA. New York, 97--106.
[4]
M. Adler, K. E. Fleming, A. Parashar, etc, "Leap scratchpads: automatic memory and cache management for reconfigurable logic," the 19th ACM/SIGDA intl. symp. FPGA, New York, NY, USA, 25--28.
[5]
G. Weisz and J. C. Hoe, "C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction, " the 19th ACM/SIGDA intl. symp. FPGA, 2013, pp. 211--230.
[6]
K. Keutzer, A. R. Newton, J. M. Rabaey, etc., "System-level design: orthogonalization of concerns and platform-based design," IEEE TCAD., vol. 19, no. 12, pp. 1523,1543, Dec 2000
[7]
A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski, and J. Teich, "Electronic system-level synthesis methodologies," IEEE TCAD, vol. 28, no. 10, pp. 1517--1530.
[8]
S. Xydis, G. Palermo, V. Zaccaria, etc., "SPIRIT: Spectral-aware Pareto Iterative Refinement Optimization for supervised high-level synthesis," IEEE TCAD, vol. 34, no. 1, pp. 155, 2015
[9]
H.-Y. Liu, and L. P. Carloni, "On learning-based methods for design-space exploration with High-Level Synthesis," ACM/EDAC/IEEE DAC, 2013, pp. 1,7, May 29, 2013
[10]
J. Cong, P. Zhang, and Y. Zou, "Optimizing memory hierarchy allocation with loop transformations for high-level synthesis," ACM/EDAC/IEEE DAC, 2012, pp. 1229,1234, 3--7 June 2012
[11]
P. Panda, F. Catthoor, etc., "Data and Memory Optimizations for Embedded Systems," ACM TODAES, 6(2):142--206,2001.
[12]
J. Cong, M. Huang, B. Liu, P. Zhang, and Y. Zou, "Combining module selection and replication for throughput-driven streaming programs," ACM/EDAC/IEEE DATE, 2012, pp. 1018,1023, 12--16 March 2012
[13]
Q. Liu, G. A. Constantinides, K. Masselos, etc., "Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: a geometric programming framework," IEEE TCAD, vol. 28, no. 3, pp. 305--315, 2009.
[14]
W. Zuo, Y. Liang, P. Li, etc., "Improving high level synthesis optimization opportunity through polyhedral transformations, " the 19th ACM/SIGDA intl. symp. FPGA, 2013, New York, NY, USA, 9--18.
[15]
C. Bastoul, "Code generation in the polyhedral model is easier than you think," the 13th International Conference on Parallel Architecture and Compilation Techniques, PACT 2014, vol., no., pp. 7,16, 29 Sept.-3 Oct. 2004
[16]
O. Shacham, S. Galal, S. Sankaranarayanan, etc., "Avoiding game over: Bringing design to the next level," Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, vol., no., pp. 623,629, 3--7 June 2012
[17]
L.-N. Pouchet, P. Zhang, P. Sadayappan, etc., "Polyhedral-based data reuse optimization for configurable computing," the ACM/SIGDA international symposium on FPGA, 2013, ACM, New York, NY, USA, 29--38.
[18]
Sx Verdoolaege, Hx Nikolov, and Tx Stefanov, "pn: a tool for improved derivation of process networks." EURASIP J. Embedded Syst. 2007, 1 (January 2007), 19--19.
[19]
A. Darte, R. Schreiber, and G. Villard, "Lattice-based memory allocation," Computers, IEEE Transactions on, vol. 54, no. 10, pp. 1242,1257, Oct. 2005

Cited By

View all
  • (2022)ChordMap: Automated Mapping of Streaming Applications Onto CGRAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305831341:2(306-319)Online publication date: Feb-2022
  • (2021)A Multi-Memory Field-Programmable Custom Computing Machine for Accelerating Compute-Intensive Applications2021 IEEE 12th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)10.1109/UEMCON53757.2021.9666601(0619-0628)Online publication date: 1-Dec-2021
  • (2021)The TaPaSCo Open-Source ToolflowJournal of Signal Processing Systems10.1007/s11265-021-01640-8Online publication date: 2-May-2021
  • Show More Cited By

Index Terms

  1. CMOST: a system-level FPGA compilation framework

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '15: Proceedings of the 52nd Annual Design Automation Conference
    June 2015
    1204 pages
    ISBN:9781450335201
    DOI:10.1145/2744769
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 07 June 2015

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. FPGA
    2. high-level synthesis
    3. system-level optimization

    Qualifiers

    • Research-article

    Funding Sources

    • NSF Expedition in Computing Award

    Conference

    DAC '15
    Sponsor:
    DAC '15: The 52nd Annual Design Automation Conference 2015
    June 7 - 11, 2015
    California, San Francisco

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)10
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 20 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2022)ChordMap: Automated Mapping of Streaming Applications Onto CGRAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305831341:2(306-319)Online publication date: Feb-2022
    • (2021)A Multi-Memory Field-Programmable Custom Computing Machine for Accelerating Compute-Intensive Applications2021 IEEE 12th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)10.1109/UEMCON53757.2021.9666601(0619-0628)Online publication date: 1-Dec-2021
    • (2021)The TaPaSCo Open-Source ToolflowJournal of Signal Processing Systems10.1007/s11265-021-01640-8Online publication date: 2-May-2021
    • (2019)Customizable Computing—From Single Chip to DatacentersProceedings of the IEEE10.1109/JPROC.2018.2876372107:1(185-203)Online publication date: Jan-2019
    • (2018)Automated accelerator generation and optimization with composable, parallel and pipeline architectureProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3195999(1-6)Online publication date: 24-Jun-2018
    • (2018)Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)10.1109/DAC.2018.8465940(1-6)Online publication date: Jun-2018
    • (2017)The Feniks FPGA Operating System for Cloud ComputingProceedings of the 8th Asia-Pacific Workshop on Systems10.1145/3124680.3124743(1-7)Online publication date: 2-Sep-2017
    • (2017)Bandwidth Optimization Through On-Chip Memory Restructuring for HLSProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062208(1-6)Online publication date: 18-Jun-2017
    • (2017)An automated Reconfigurable-Computing Environment for accelerating software applicationsSoutheastCon 201710.1109/SECON.2017.7925338(1-7)Online publication date: Mar-2017
    • (2016)Composable, parameterizable templates for high-level synthesisProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971979(744-749)Online publication date: 14-Mar-2016
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media