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Design for low test pattern counts

Published: 07 June 2015 Publication History

Abstract

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

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  • (2024)SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard ScanACM Transactions on Design Automation of Electronic Systems10.1145/369819830:1(1-13)Online publication date: 8-Nov-2024
  • (2024)Functional Design-for-Testability for Functional Test SequencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339665443:12(4852-4859)Online publication date: Dec-2024
  • (2024)A Hybrid Test Point Insertion Strategy for Improved Test Metrics2024 IEEE 8th International Test Conference India (ITC India)10.1109/ITCIndia62949.2024.10651966(1-7)Online publication date: 21-Jul-2024
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cover image ACM Conferences
DAC '15: Proceedings of the 52nd Annual Design Automation Conference
June 2015
1204 pages
ISBN:9781450335201
DOI:10.1145/2744769
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2015

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Author Tags

  1. design for testability
  2. scan-based test
  3. test data compression

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DAC '15: The 52nd Annual Design Automation Conference 2015
June 7 - 11, 2015
California, San Francisco

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Cited By

View all
  • (2024)SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard ScanACM Transactions on Design Automation of Electronic Systems10.1145/369819830:1(1-13)Online publication date: 8-Nov-2024
  • (2024)Functional Design-for-Testability for Functional Test SequencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339665443:12(4852-4859)Online publication date: Dec-2024
  • (2024)A Hybrid Test Point Insertion Strategy for Improved Test Metrics2024 IEEE 8th International Test Conference India (ITC India)10.1109/ITCIndia62949.2024.10651966(1-7)Online publication date: 21-Jul-2024
  • (2024)Functional Compaction for Functional Test SequencesIEEE Access10.1109/ACCESS.2024.342924812(98130-98140)Online publication date: 2024
  • (2023)Diagnostic Test Point Insertion and Test CompactionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.321892431:2(276-285)Online publication date: Feb-2023
  • (2023)A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy2023 IEEE International Test Conference (ITC)10.1109/ITC51656.2023.00010(1-10)Online publication date: 7-Oct-2023
  • (2020)Reverse Low-Power Broadside TestsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289467539:3(742-746)Online publication date: Mar-2020
  • (2019)Extended Transparent-ScanIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291649727:9(2096-2104)Online publication date: Sep-2019
  • (2019)Logic BIST With Capture-Per-Clock Hybrid Test PointsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283444138:6(1028-1041)Online publication date: 1-Jun-2019
  • (2019)Improved Test Coverage by Observation Point Insertion for Fault Coverage Analysis2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI)10.1109/ICOEI.2019.8862789(174-178)Online publication date: Apr-2019
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