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Domain wall memory based digital signal processors for area and energy-efficiency

Published: 07 June 2015 Publication History

Abstract

In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

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Cited By

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  • (2018)Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.018117:C(127-137)Online publication date: 1-Jul-2018
  • (2016)Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor DesignIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.249755863:1(91-102)Online publication date: Jan-2016
  • (2016)Overview of Circuits, Systems, and Applications of SpintronicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.26013106:3(265-278)Online publication date: Sep-2016

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        cover image ACM Conferences
        DAC '15: Proceedings of the 52nd Annual Design Automation Conference
        June 2015
        1204 pages
        ISBN:9781450335201
        DOI:10.1145/2744769
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 07 June 2015

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        Author Tags

        1. STT-MRAM
        2. digital signal processor
        3. domain wall memory
        4. embedded memory

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        DAC '15: The 52nd Annual Design Automation Conference 2015
        June 7 - 11, 2015
        California, San Francisco

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        View all
        • (2018)Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.018117:C(127-137)Online publication date: 1-Jul-2018
        • (2016)Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor DesignIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.249755863:1(91-102)Online publication date: Jan-2016
        • (2016)Overview of Circuits, Systems, and Applications of SpintronicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.26013106:3(265-278)Online publication date: Sep-2016

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