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High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Published: 07 June 2015 Publication History

Abstract

In this study, we propose a low-cost approach to error detection for arithmetic orientated data paths by performing lightweight shadow computations in modulo-3 space for each main computation. By leveraging the binding and scheduling flexibility of high-level synthesis, we detect errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We evaluated our technique with 12 high-level synthesis benchmarks using FPGA emulated netlist-level error injection. We observe coverages of 99.13% for stuck-at faults, 99.46% for soft errors, and 99.67% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging error detection latencies on the order of 10 cycles (3 orders of magnitude faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors.

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Cited By

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  • (2022)Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS56730.2022.9897824(1-8)Online publication date: 12-Sep-2022
  • (2021)Reducing the Complexity of Fault-Tolerant System amenable to Approximate Computing2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401605(1-5)Online publication date: May-2021
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  1. High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

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          cover image ACM Conferences
          DAC '15: Proceedings of the 52nd Annual Design Automation Conference
          June 2015
          1204 pages
          ISBN:9781450335201
          DOI:10.1145/2744769
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Publication History

          Published: 07 June 2015

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          Author Tags

          1. aliasing
          2. automation
          3. binding
          4. checkpointing
          5. datapath
          6. electrical faults
          7. error detection
          8. high performance
          9. high-level synthesis
          10. logic optimization
          11. low cost
          12. modulo arithmetic
          13. optimization
          14. pipelining
          15. rollback recovery
          16. scheduling
          17. shadow logic
          18. soft errors
          19. state machine
          20. stuck-at faults
          21. timing errors

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          DAC '15: The 52nd Annual Design Automation Conference 2015
          June 7 - 11, 2015
          California, San Francisco

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          Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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          Cited By

          View all
          • (2022)A High-Level Synthesis Methodology for Energy and Reliability-Oriented DesignsIEEE Transactions on Computers10.1109/TC.2020.304388571:1(161-174)Online publication date: 1-Jan-2022
          • (2022)Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS56730.2022.9897824(1-8)Online publication date: 12-Sep-2022
          • (2021)Reducing the Complexity of Fault-Tolerant System amenable to Approximate Computing2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401605(1-5)Online publication date: May-2021
          • (2021)High-Level Synthesis for Minimizing Power Side-Channel Information LeakageBehavioral Synthesis for Hardware Security10.1007/978-3-030-78841-4_13(291-317)Online publication date: 28-May-2021
          • (2020)Cross-Layer Resilience Against Soft Errors: Key InsightsDependable Embedded Systems10.1007/978-3-030-52017-5_11(249-275)Online publication date: 10-Dec-2020
          • (2019)An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant ArithmeticJournal of Circuits, Systems and Computers10.1142/S021812661950244X28:14(1950244)Online publication date: 26-Mar-2019
          • (2019)Cost-Effective Error Detection Through Mersenne Modulo Shadow DatapathsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283441738:6(1056-1069)Online publication date: 1-Jun-2019
          • (2018)Evaluating and accelerating high-fidelity error injection for HPCProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.5555/3291656.3291716(1-13)Online publication date: 11-Nov-2018
          • (2018)Low-cost hardware architectures for mersenne modulo functional unitsProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201746(599-604)Online publication date: 22-Jan-2018
          • (2018)Evaluating and accelerating high-fidelity error injection for HPCProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC.2018.00048(1-13)Online publication date: 11-Nov-2018
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