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Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks

Published: 07 June 2015 Publication History

Abstract

In this paper, we investigate an intriguing shifting trend in performance bottlenecks for Near-Threshold Computing (NTC) processors. Our study demonstrates that the traditional memory latency bottleneck is largely superseded by the bottlenecks of Long Latency Datapaths (LLDs) within a processor core. To exploit this paradigm shift, we propose Opportunistic Turbo Execution (OTE). OTE dynamically boosts the performance of LLDs, by several factors, improving both performance and energy efficiency in an NTC core. Using a comprehensive circuit-architectural analysis, we demonstrate a 42.2% improvement in energy efficiency over a recently proposed technique, across a range of benchmarks.

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Cited By

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  • (2020)Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing ErrorsJournal of Low Power Electronics and Applications10.3390/jlpea1004003310:4(33)Online publication date: 16-Oct-2020
  • (2020)Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) CachesDependable Embedded Systems10.1007/978-3-030-52017-5_13(303-334)Online publication date: 10-Dec-2020
  • (2019)A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281869138:3(439-452)Online publication date: Mar-2019
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        cover image ACM Conferences
        DAC '15: Proceedings of the 52nd Annual Design Automation Conference
        June 2015
        1204 pages
        ISBN:9781450335201
        DOI:10.1145/2744769
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 07 June 2015

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        June 7 - 11, 2015
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        Cited By

        View all
        • (2020)Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing ErrorsJournal of Low Power Electronics and Applications10.3390/jlpea1004003310:4(33)Online publication date: 16-Oct-2020
        • (2020)Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) CachesDependable Embedded Systems10.1007/978-3-030-52017-5_13(303-334)Online publication date: 10-Dec-2020
        • (2019)A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281869138:3(439-452)Online publication date: Mar-2019
        • (2017)Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.266937525:7(2017-2026)Online publication date: Jul-2017
        • (2016)A cross-layer analysis of soft error, aging and process variation in near threshold computingProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971854(205-210)Online publication date: 14-Mar-2016
        • (2016)Temperature-aware Dynamic Voltage Scaling for Near-Threshold ComputingProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902997(361-364)Online publication date: 18-May-2016

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