research-article

Physically aware high level synthesis design flow

Authors:

Tsuyoshi TakabatakeAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 162, Pages 1 - 6

https://doi.org/10.1145/2744769.2744893

Published: 07 June 2015 Publication History

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Abstract

High Level Synthesis (HLS) has many productivity advantages over traditional RTL design, but routing congestion is difficult to resolve due to the lack of physical information in HLS. In this paper we propose a novel design flow by integrating a HLS tool with physically aware logic synthesis technology. Using this approach, one can discover congestion problems early and trace their sources to specific parts of the input SystemC models. This allows designers to resolve the congestion problems before going to the layout design phase. We applied this flow to a large-scale HLS production design with results showing that this flow can significantly improve not only routing congestion but design area and timing as well.

References

[1]

J. Wu, C. Ma, and B. Huang, Congestion Aware High Level Synthesis Combined with Floorplanning, PACIIA'08, Pages 935--938, 2008.

Digital Library

Google Scholar

[2]

J. Cong, B. Liu, G. Luo, and R. Prabhakar. Towards Layout-Friendly High Level Synthesis. ISPD'12, Pages 165--172, 2012.

Digital Library

Google Scholar

[3]

J. Cong, and B. LiuA. Metric for Layout-Friendly Microarchitecture Optimization in High Level Synthesis. DAC'12, Pages 1239--1244, 2012.

Digital Library

Google Scholar

[4]

J. Um, J. Kim, and T. Kim, Layout-Driven Resource Sharing in High-Level Synthesis. ICCAD'02, Pages 614--618, 2002.

Digital Library

Google Scholar

[5]

M. Clarke, D. Hammerschlag, M. Rardon and A. Sood. Eliminating Routing Congestion Issues with Logic Synthesis. Cadence White Paper, http://www.cadence.com/rl/resources/white_papers/routing_congestion_wp.pdf

Google Scholar

[6]

Y. Wang, J. Bian, Q. Wu and H, Hu. Reallocation and Rescheduling after floor-planning for timing optimization. ASIC'03, Pages 212--215, 2003.

Google Scholar

[7]

D. Pandini, L. T. Pileggi and A. J. Strojwas. Congestion aware logic synthesis. DATE'02, Pages 664--671 2002.

Digital Library

Google Scholar

[8]

V. Sundaresan and R. Vemuri. A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. ISVLSI'06, 2006.

Digital Library

Google Scholar

[9]

J. Pin and A. C. Parker. 3D Scheduling: High-Level Synthesis with Floorplaning. DAC'91, Pages 668--673, 1991.

Digital Library

Google Scholar

[10]

S. Trafdar, M. Leeser, and Z. Yin. Integrating Floorplanning In Data-Transfer Based High-Level Synthesis. ICCAD'98, Pages 412--417, 1998.

Digital Library

Google Scholar

[11]

V. G. Moshnyaga and K. Tamaru. A Placement Driven Methodology For f High-Level Synthesis of Sub-Micron ASIC's. ISCAS'96, Pages 572--575, 1996.

Crossref

Google Scholar

[12]

Encounter RTL Complier Advanced Physical Option DataSheet (RCP), http://www.cadence.com/rl/Resources/datasheets/rtl_physical_ds.pdf

Google Scholar

[13]

C-to-Silicon Compiler, http://www.cadence.com/products/sd/silicon_compiler/pages/default.aspx

Google Scholar

[14]

Accellera Systems Initiative, http://www.accellera.org/downloads/standards/systemc

Google Scholar

Cited By

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Xing DSrivastava ADe V(2024)A High Level Approach to Co-Designing 3D ICsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658268(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658268
Guo XZhao XZhu L(2024)Integration of Shift-Left Updates into Logic Synthesis and Macro Placement2024 Conference of Science and Technology for Integrated Circuits (CSTIC)10.1109/CSTIC61820.2024.10531906(1-3)Online publication date: 17-Mar-2024
https://doi.org/10.1109/CSTIC61820.2024.10531906
Zhu LGuo X(2023)Delay-Driven Physically-Aware Logic Synthesis with Informed Search2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00057(327-335)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00057
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Index Terms

Physically aware high level synthesis design flow
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Physical design (EDA)
  2. Hardware validation

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Published In

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Xing DSrivastava ADe V(2024)A High Level Approach to Co-Designing 3D ICsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658268(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658268
Guo XZhao XZhu L(2024)Integration of Shift-Left Updates into Logic Synthesis and Macro Placement2024 Conference of Science and Technology for Integrated Circuits (CSTIC)10.1109/CSTIC61820.2024.10531906(1-3)Online publication date: 17-Mar-2024
https://doi.org/10.1109/CSTIC61820.2024.10531906
Zhu LGuo X(2023)Delay-Driven Physically-Aware Logic Synthesis with Informed Search2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00057(327-335)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00057
Maestre SGumera AHora Jde Guzman M(2022)Improving Digital Design PPA (Performance, Power, Area) using iSpatial Physical Restructuring2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)10.1109/ITC-CSCC55581.2022.9895022(647-651)Online publication date: 5-Jul-2022
https://doi.org/10.1109/ITC-CSCC55581.2022.9895022
Tariq OShan JFloros GSotiriou CCasu MLazarescu MLavagno L(2021)High-Level Annotation of Routing Congestion for Xilinx Vivado HLS DesignsIEEE Access10.1109/ACCESS.2021.30674539(54286-54297)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3067453
Heldmann TSchneider TTkachenko OWeinert CYalame H(2021)LLVM-Based Circuit Compilation for Practical Secure ComputationApplied Cryptography and Network Security10.1007/978-3-030-78375-4_5(99-121)Online publication date: 10-Jun-2021
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TATSUOKA MKANEKO M(2020)High Level Congestion Detection from C/C++ Source Code for High Level SynthesisIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2020VLP0012E103.A:12(1437-1446)Online publication date: 1-Dec-2020
https://doi.org/10.1587/transfun.2020VLP0012
Guo LLau JChi YWang JYu CChen ZZhang ZCong J(2020)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218718(1-6)Online publication date: Jul-2020
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Zhao JLiang TSinha SZhang W(2019)Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714724(1130-1135)Online publication date: Mar-2019
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Tatsuoka MKaneko M(2018)Wire congestion aware high level synthesis flow with source code compiler2018 International Conference on IC Design & Technology (ICICDT)10.1109/ICICDT.2018.8399766(101-104)Online publication date: Jun-2018
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High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

A high-level synthesis based VLSI design methodology

High-Level Synthesis: Past, Present, and Future

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