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RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory

Published: 07 June 2015 Publication History

Abstract

Refresh operations consume substantial energy and bandwidth in high-density DRAM memory. To cope with this issue, Fine-Grained Refresh (FGR) is recently proposed to eliminate unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR to make DRAM refresh more scalable. Unfortunately, we observe that the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this work, we firstly propose to intelligently integrate the "compatible" devices through a pre-assembly testing and retention-aware matching method. Second, we reuse the reconfiguration structure from yield-oriented remapping mechanism in memory chips and propose Microfix to create a balanced distribution of retention time in memory banks through fine-grained row-address tuning. With this optimization architecture, RADAR, we can eliminate the refresh overhead of produced memory modules by 28% on average.

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  • (2023)Architecture-Aware Currying2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00029(250-264)Online publication date: 21-Oct-2023
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  1. RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory

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      cover image ACM Conferences
      DAC '15: Proceedings of the 52nd Annual Design Automation Conference
      June 2015
      1204 pages
      ISBN:9781450335201
      DOI:10.1145/2744769
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 07 June 2015

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      View all
      • (2023)Architecture-Aware Currying2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00029(250-264)Online publication date: 21-Oct-2023
      • (2022)KrakenOnMemProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532367(1-14)Online publication date: 28-Jun-2022
      • (2019)Workload-Aware DRAM Error Prediction using Machine Learning2019 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC47752.2019.9041963(106-118)Online publication date: Nov-2019
      • (2019)Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAMJournal of Electronic Testing10.1007/s10836-019-05817-9Online publication date: 13-Aug-2019
      • (2018)The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00026(194-207)Online publication date: Feb-2018
      • (2017)The Reach Profiler (REAPER)ACM SIGARCH Computer Architecture News10.1145/3140659.308024245:2(255-268)Online publication date: 24-Jun-2017
      • (2017)The Reach Profiler (REAPER)Proceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080242(255-268)Online publication date: 24-Jun-2017
      • (2017)On the Restore Time Variations of Future DRAM MemoryACM Transactions on Design Automation of Electronic Systems10.1145/296760922:2(1-24)Online publication date: 9-Feb-2017
      • (2017)Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power2017 International Test Conference in Asia (ITC-Asia)10.1109/ITC-ASIA.2017.8097121(101-106)Online publication date: Sep-2017

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