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SuperNet: multimode interconnect architecture for manycore chips

Published: 07 June 2015 Publication History

Abstract

Designers of the on-chip interconnect for manycore chips are faced with the dilemma of meeting performance, power and reliability requirements for different operational scenarios. In this paper, we propose a multimode on-chip interconnect called SuperNet. This interconnect can be configured to run in three different modes: energy efficient mode; performance mode; and, reliability mode. Our proposed interconnect is based on two parallel multi-vt optimized packet switched network-on-chip (NoC) meshes. We describe the circuit design techniques and architectural modifications required to realize such a multimode interconnect. Our evaluation with diverse set of applications show that the energy efficient mode can save on average 40% NoC power, whereas the performance mode can improve the core IPC by up to 13% on selected high MPKI applications. The reliability mode provides protection against soft errors in the router's data path through byte oriented SECDED codes that can correct up to 8 bit errors and detect up to 16 bit errors in a 64 bit flit, whereas the router's control path is protected through DMR lock step execution.

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  • (2021)Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)10.1109/DTIS53253.2021.9505053(1-6)Online publication date: 28-Jun-2021
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    cover image ACM Conferences
    DAC '15: Proceedings of the 52nd Annual Design Automation Conference
    June 2015
    1204 pages
    ISBN:9781450335201
    DOI:10.1145/2744769
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 07 June 2015

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    Author Tags

    1. fault tolerance
    2. multimode
    3. network-on-chip
    4. performance
    5. power optimization

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    June 7 - 11, 2015
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    View all
    • (2024)SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473870(13-18)Online publication date: 22-Jan-2024
    • (2021)Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)10.1109/DTIS53253.2021.9505053(1-6)Online publication date: 28-Jun-2021
    • (2021)Power efficient network selector placement in control plane of multiple networks-on-chipThe Journal of Supercomputing10.1007/s11227-021-04098-478:5(6664-6695)Online publication date: 25-Oct-2021
    • (2019)Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers DesignSensors10.3390/s1924541619:24(5416)Online publication date: 9-Dec-2019
    • (2019)Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router2019 IEEE Latin American Test Symposium (LATS)10.1109/LATW.2019.8704580(1-6)Online publication date: Mar-2019
    • (2018)A Customized Authentication Design for Traffic Hijacking Detection on Hardware-Trojan Infected NoCsJournal of Computer and Communications10.4236/jcc.2018.6101506:01(135-152)Online publication date: 2018
    • (2018)Hybrid Network-on-ChipComplexity10.1155/2018/10408692018Online publication date: 30-Jul-2018
    • (2018)A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)10.1109/iSES.2018.00060(243-248)Online publication date: Dec-2018
    • (2018)EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00070(345-350)Online publication date: Jul-2018
    • (2018)Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351501(1-5)Online publication date: May-2018
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