research-article

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

Authors:

Shreepad Panth,

Kambiz Samadi,

Yang Du,

Sung Kyu LimAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 92, Pages 1 - 6

https://doi.org/10.1145/2744769.2744917

Published: 07 June 2015 Publication History

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Abstract

Power delivery to the tier farthest away from the package in 3D VLSI is challenging. This is because the current provided by the package on the bottom is (1) first used by other tiers before it reaches the top, and (2) delivered using extremely small-size intra and inter-tier vias. Our solution is a tier partitioning method that assigns power hungry cells to the tier closer to the package, which is farther away from the heat spreader. Our study shows that this approach alleviates the IR-drop, power delivery network (PDN) resource usage, and power consumption in the top tier. Moreover, moving the cells to the bottom tier, unlike popular belief, does not cause any serious thermal issues. This is especially true in mobile applications, where heat is dissipated by both the heat spreader and printed circuit board. In summary, our tier-partitioning leads to 24.66% IR-drop reduction, 28.57% PDN resource reduction, and 4% wirelength reduction, with < 1°C increase in temperature.

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Personal communication with industry partner.

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Cited By

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Kahng AKang SKim SXu B(2021)Enhanced Power Delivery Pathfinding for Emerging 3-D Integration TechnologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304166529:4(591-604)Online publication date: Apr-2021
https://doi.org/10.1109/TVLSI.2020.3041665
Kahng AKang SKim SSamadi KXu B(2019)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715046(842-847)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715046
Koneru ATodri-Sanial AChakrabarty K(2019)Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758650(1-6)Online publication date: Apr-2019
https://doi.org/10.1109/VTS.2019.8758650
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Index Terms

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications
1. Hardware
  1. Hardware validation

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DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

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Kahng AKang SKim SXu B(2021)Enhanced Power Delivery Pathfinding for Emerging 3-D Integration TechnologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304166529:4(591-604)Online publication date: Apr-2021
https://doi.org/10.1109/TVLSI.2020.3041665
Kahng AKang SKim SSamadi KXu B(2019)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715046(842-847)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715046
Koneru ATodri-Sanial AChakrabarty K(2019)Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758650(1-6)Online publication date: Apr-2019
https://doi.org/10.1109/VTS.2019.8758650
Koneru ATodri-Sanial AChakrabarty K(2018)Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2018.8617951(217-220)Online publication date: Dec-2018
https://doi.org/10.1109/ICECS.2018.8617951
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604
Samal SSamadi KKamal PDu YLim S(2017)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261637736:6(992-1003)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2616377
Samal SPanth SSamadi KSaeidi MDu YLim S(2016)Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252398335:10(1707-1720)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2523983

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Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs

Peak power identification on power bumps during test application

Cooling mechanisms in 3D ICs: Thermo-mechanical perspective

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