research-article

3DIC benefit estimation and implementation guidance from 2DIC implementation

Authors:

Wei-Ting J. Chan,

Siddhartha Nath,

Andrew B. Kahng,

Kambiz SamadiAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 30, Pages 1 - 6

https://doi.org/10.1145/2744769.2747954

Published: 07 June 2015 Publication History

Abstract

Quantification of three-dimensional integrated circuit (3DIC) benefits over corresponding 2DIC implementation for arbitrary designs remains a critical open problem, largely due to nonexistence of any "golden" 3DIC flow. Actual design and implementation parameters and constraints affect 2DIC and 3DIC final metrics (power, slack, etc.) in highly non-monotonic ways that are difficult for engineers to comprehend and predict. We propose a novel machine learning-based methodology to estimate 3DIC power benefit (i.e., percentage power reduction) based on corresponding golden 2DIC implementation parameters. The resulting 3D Power Estimation (3DPE) models achieve small prediction errors that are bounded by construction. We are the first to perform a novel stress test of our predictive models across a wide range of implementation and design-space parameters. Further, we explore model-guided implementation of designs in 3D to achieve minimum power: that is, our models recommend a most-promising set of implementation parameters and constraints, and also provide a priori estimates of 3D power benefits, based on a given design's post-synthesis and 2D implementation parameters. We achieve ≤10% error in power benefit prediction across various 3DIC designs.

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Cited By

Kahng AKang SKim SSamadi KXu B(2019)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715046(842-847)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715046
Yi MBian JNi TJiang CChang HLiang H(2019)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.282155938:4(755-766)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2821559
Kahng AShin Y(2018)New directions for learning-based IC design tools and methodologiesProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201708(405-410)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201708
Show More Cited By

Index Terms

3DIC benefit estimation and implementation guidance from 2DIC implementation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Kahng AKang SKim SSamadi KXu B(2019)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715046(842-847)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715046
Yi MBian JNi TJiang CChang HLiang H(2019)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.282155938:4(755-766)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2821559
Kahng AShin Y(2018)New directions for learning-based IC design tools and methodologiesProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201708(405-410)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201708
Kang IQiao FPark DKane DYoung ECheng CGraham R(2018)Three-dimensional Floorplan Representations by Using Corner Links and Partial OrderACM Transactions on Design Automation of Electronic Systems10.1145/328917924:1(1-33)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3289179
Hong IKim D(2018)Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276842737:8(1614-1626)Online publication date: Aug-2018
https://doi.org/10.1109/TCAD.2017.2768427
Samal SSamadi KKamal PDu YLim S(2017)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261637736:6(992-1003)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2616377
Chan WKahng ALi J(2017)Revisiting 3DIC benefit with multiple tiersIntegration10.1016/j.vlsi.2017.01.00458(226-235)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.01.004
Chan WKahng ALi JTaskin BHo T(2016)Revisiting 3DIC Benefit with Multiple TiersProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947363(1-8)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947363
Samal SNayak Dlchihashi MBanna SLim S(2016)How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICsProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934643(320-325)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934643
Kahng AKoushanfar FMarculescu DLiu F(2015)Evolving EDA Beyond its E-RootsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840855(247-254)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840855

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