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Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles

Published: 07 June 2015 Publication History

Abstract

Post-silicon validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address post-silicon validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the Hybrid Quick Error Detection (H-QED) approach that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it manifests as an observable failure) by 2 orders of magnitude and bug coverage 3-fold compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 2% chip-level area overhead with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.

References

[1]
{Abramovici 08} M. Abramovici, "In-System Silicon Validation and Debug," IEEE Design & Test of Computers, Vol. 25, No. 3, pp. 216--223, May 2008.
[2]
{Adir 11} Adir, A., et al., "Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors," DAC, 2011.
[3]
{ARM CoreSight} ARM CoreSight, http://www.arm.com/products/system-ip/coresight.
[4]
{Austin 99} Austin, T. M., "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," Proc. IEEE/ACM MICRO, pp. 196--207, 1999.
[5]
{Bohr 09} "The New Era of Scaling in an SoC World," Proc. ISSCC 2009.
[6]
{C11} International Organization for Standardization, "ISO/IEC 9899:201x - Programming languages - C," Dec 2011.
[7]
{Feng 06} Feng, X., and A. J. Hu, "Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification," DAC, pp. 1063--1068, 2006.
[8]
{Friedler 14} Friedler, O., et al., "Effective Post-Silicon Failure Localization Using Dynamic Program Slicing," DATE, pp. 1--6, 2014.
[9]
{Fujigaya 13} M. Fujigaya, et al., "A 28nm High-κ Netal-Gate Single-Chip Communications Processor with 1.5GHz Dual-Core Application Processor and LTE/HSPA+-Capable Baseband Processor," Proc. Intl. Solid State Circuits Conf., pp. 156--157, Feb. 2013.
[10]
{Fujita 05} Fujita, M., "Equivalence Checking Between Behavioral and RTL Descriptions with Virtual Controllers and Datapaths," ACM Trans. Design Automation Electronic Systems, Vol. 10, No. 4, pp. 610--626, Oct. 2005.
[11]
{Gao 12} M. Gao, et al., "On Error Modeling of Electrical Bugs for Post-silicon Timing Validation," ASPDAC, pp. 701--706, 2012.
[12]
{Gray 85} Gray, J., "Why Do Computers Stop and What Can Be Done About It?" Tandem Computer, Tech. Report 85.7, PN 87614, 1985.
[13]
{Hara 09} Y. Hara, et al., "Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis", Information Processing, 2009.
[14]
{Ho 09} Ho, R. C., et al., "Post-Silicon Debug Using Formal Verification Waypoints," Proc. Design Validation Conf., 2009.
[15]
{Hong 10} Hong, T., et al., "QED: Quick Error Detection Tests for Effective Post-Silicon Validation," Proc. IEE/ACM Intl. Test Conf., pp. 1--10, 2010.
[16]
{Karri 93} Karri, R., A. Orailoglu, "High-Level Synthesis of Fault-Secure Microarchitectures," DAC, pp. 429--433, 1993.
[17]
{Lattner 04} C. Lattner and V. Adve, "LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation," CGO, pp. 75--86, 2004.
[18]
{Lattner 11} C. Lattner "LLVM and Clang: Advancing Compiler Technology", Keynote Talk, FOSDEM, 2011.
[19]
{Lin 12} Lin, D., et al., "Quick Detection of Difficult Bugs for Effective Post-Silicon Validation," DAC, pp. 561--566, 2012.
[20]
{Lin 14} Lin, D., et al., "Effective Post-Silicon of System-on-Chips Using Quick Error Detection," IEEE Trans. CAD, Vol. 33, No. 10, pp. 1573--1590, Oct. 2014.
[21]
{Lin 15} Lin, D., et al., Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug, DATE, 2015.
[22]
{Lu 82} D. J. Lu, "Watchdog Processors and Structural Integrity Checking", IEEE. Trans. Computers, Vol. 31, No. 7, pp. 681--685, Jul. 1982.
[23]
{Mathur 09} Mathur, A., et al., "Functional Equivalence Verification Tools in High-Level Synthesis Flows," Proc. IEEE Design and Test of Computers, pp. 88--95, 2009.
[24]
{Mahmood 88} Mahmood, A., and E. J. McCluskey, "Concurrent Error Detection Using Watchdog Processors -- A Survey," IEEE Trans. Computers, Vol. 37, No. 2, pp. 160--174, Feb. 1988.
[25]
{Mitra 00} Mitra, S., N. R. Saxena and E. J. McCluskey, "Fault Escapes in Duplex Systems," Proc. IEEE VLSI Test Symp., pp. 453--458, 2000.
[26]
{Mitra 10} Mitra, S., S. A. Seshia, and N. Nicolici, "Post-Silicon Validation Opportunities, Challenges and Recent Advances," DAC, pp. 12--17, 2010.
[27]
{Martin 09} G. Martin and G. Smith, "High-Level Synthesis: Past, Present, and Future," IEEE Design & Test of Computers, Vol: 26, Issue:4, 2009.
[28]
{Park 09} Park, S.-B., T. Hong, and S. Mitra, "Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)," IEEE. Trans. CAD, pp. 1545--1558, Oct. 2009.
[29]
{Park 10} Park, S.-B., et al., "BLoG: Post-Silicon Bug Localization in Processors Using Bug Localization Graph," DAC, pp. 368--373, 2010.
[30]
{Pouchet 12} L. N. Pouchet. PolyBench/C 3.2. http://www.cse.ohio-state.edu/~pouchet/software/polybench/
[31]
{Reick 12} Reick, K., "Post-Silicon Debug," DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices. DAC, 2012.
[32]
{Rupnow 11} K. Rupnow, Y. Liang, Y. Li, and D. Chen, "A Study of High-Level Synthesis: Promises and Challenges," Proc. IEEE Intl. Conf. on ASIC, pp. 1102--1105, 2011.
[33]
{Saxena 00} Saxena, N. R., S. Fernandez-Gomez, W. J. Huang, S. Mitra, S.-Y. Yu and E. J. McCluskey, Saxena, N. R., S. Fernand, Online Testing in Adaptive and Configurable Systems, IEEE Design and Test of Computers, Vol. 17, No. 1, pp. 29--41, Jan.--Mar. 2000.
[34]
{Saxena 98} Saxena, N. R., and E. J. McCluskey, "Dependable Adaptive Computing Systems, c Proc. IEEE Systems, Man, and Cybernetics Conf., pp. 2172--2177, 1998.
[35]
{Smolens 04} Smolens, J. C., et al., "Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth," Proc. ACM ASPLOS, pp. 224--234, 2004.
[36]
{Sogomonyan 01} Sogomoyan, E. S., et al., "Early Error Detection in System-on-Chip for Fault-Tolerance and At-Speed Debugging," Proc. IEEE VLSI Test Symp., pp. 184--189, 2001.
[37]
{Wagner 08} Wagner, I., and V. Bertacco, "Reversi: Post-Silicon Validation System for Modern Microprocessors," ICCD 2008.
[38]
{Wakabayashi 00} Wakabayashi, K., and T. Okamoto, "C-based SoC Design Flow and EDA Tools: An ASIC and System Vendor Perspective," Proc IEEE Trans. CAD, Vol. 19, No. 12, pp. 1507--1522, Dec. 2000.
[39]
{Wakabayashi 04} Wakabayashi, K., "C-Based Behavioral Synthesis and Verification Analysis on Industrial Design Examples," Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., pp. 344--348, 2004.
[40]
{Yang 09} Y. Yang, N. Nicolici, and A. Veneris, "Automated Data Analysis Solutions to Silicon Debug," Proc. IEEE/ACM Design Automation Test in Europe, pp. 982--987, 2009.
[41]
{Yerramilli 06} Yerramilli, S., "Addressing Post-Silicon Validation Challenges: Leverage Validation & Test Synergy," Keynote, ITC 2006.

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cover image ACM Conferences
DAC '15: Proceedings of the 52nd Annual Design Automation Conference
June 2015
1204 pages
ISBN:9781450335201
DOI:10.1145/2744769
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2015

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Author Tags

  1. C simulation
  2. accelerators
  3. high-level synthesis
  4. logic bugs
  5. post-silicon validation
  6. signature generation
  7. timing errors

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DAC '15: The 52nd Annual Design Automation Conference 2015
June 7 - 11, 2015
California, San Francisco

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Cited By

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  • (2023)Optimization on operation sorting for HLS scheduling algorithmsIntegration10.1016/j.vlsi.2023.10205893(102058)Online publication date: Nov-2023
  • (2020)A Survey on Performance Optimization of High-Level Synthesis ToolsJournal of Computer Science and Technology10.1007/s11390-020-9414-835:3(697-720)Online publication date: 29-May-2020
  • (2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
  • (2017)Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level SynthesisACM Transactions on Embedded Computing Systems10.1145/312656416:5s(1-19)Online publication date: 27-Sep-2017
  • (2017)New advances of high-level synthesis for efficient and reliable hardware designIntegration10.1016/j.vlsi.2016.11.00658(189-214)Online publication date: Jun-2017
  • (2016)Unified Coverage Methodology for SoC Post-Silicon ValidationOptics and Photonics Journal10.4236/opj.2016.61002606:10(261-268)Online publication date: 2016
  • (2016)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898002(1-6)Online publication date: 5-Jun-2016
  • (2016)Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked QuestionsIEEE Design & Test10.1109/MDAT.2016.259098733:6(55-62)Online publication date: Dec-2016
  • (2016)Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs2016 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2016.7929514(109-116)Online publication date: Dec-2016
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