skip to main content
10.1145/2749469.2750388acmconferencesArticle/Chapter ViewAbstractPublication PagesiscaConference Proceedingsconference-collections
research-article

Hi-fi playback: tolerating position errors in shift operations of racetrack memory

Published: 13 June 2015 Publication History

Abstract

Racetrack memory is an emerging non-volatile memory based on spintronic domain wall technology. It can achieve ultra-high storage density. Also, its read/write speed is comparable to that of SRAM. Due to the tape-like structure of its storage cell, a "shift" operation is introduced to access racetrack memory. Thus, prior research mainly focused on minimizing shift latency/energy of racetrack memory while leveraging its ultra-high storage density. Yet the reliability issue of a shift operation, however, is not well addressed. In fact, racetrack memory suffers from unsuccessful shift due to domain misalignment. Such a problem is called "position error" in this work. It can significantly reduce mean-time-to-failure (MTTF) of racetrack memory to an intolerable level. Even worse, conventional error correction codes (ECCs), which are designed for "bit errors", cannot protect racetrack memory from the position errors.
In this work, we investigate the position error model of a shift operation and categorize position errors into two types: "stop-in-middle" error and "out-of-step" error. To eliminate the stop-in-middle error, we propose a technique called sub-threshold shift (STS) to perform a more reliable shift in two stages. To detect and recover the out-of-step error, a protection mechanism called position error correction code (p-ECC) is proposed. We first describe how to design a p-ECC for different protection strength and analyze corresponding design overhead. Then, we further propose how to reduce area cost of p-ECC by leveraging the "overhead region" in a racetrack memory stripe. With these protection mechanisms, we introduce a position-error-aware shift architecture. Experimental results demonstrate that, after using our techniques, the overall MTTF of racetrack memory is improved from 1.33μs to more than 69 years, with only 0:2% performance degradation. Trade-off among reliability, area, performance, and energy is also explored with comprehensive discussion.

References

[1]
"Amd eighth-generation processor architecture." ADVANCED MICRO DEVICES, October 2001. {Online}. Available: http://intel80386.com/amd/k8_architecture.pdf
[2]
"Ultrasparc iv processor architecture overview technical whitepaper." SUN microsystems, February 2004. {Online}. Available: http://laser.cbs.cnrs.fr/IMG/pdf/SUN-usiv-arch.pdf
[3]
"Intel pentium 4 processor on 90nm process datasheet." INTEL, February 2005. {Online}. Available: http://download.intel.com/design/Pentium4/datashts/30056103.pdf
[4]
A. R. Alameldeen, I. Wagner, Z. Chishti, W. Wu, C. Wilkerson, and S.-L. Lu, "Energy-efficient cache design using variable-strength error-correcting codes," in Proceedings of the 38th Annual International Symposium on Computer Architecture, ser. ISCA '11. New York, NY, USA: ACM, 2011, pp. 461--472. {Online}. Available: http://doi.acm.org/10.1145/2000064.2000118
[5]
C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The parsec benchmark suite: Characterization and architectural implications," Princeton University, Tech. Rep. TR-811-08, January 2008.
[6]
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, "The gem5 simulator," SIGARCH Comput. Archit. News, vol. 39, no. 2, pp. 1--7, Aug. 2011. {Online}. Available: http://doi.acm.org/10.1145/2024716.2024718
[7]
D. Bossen, J. M. Tendler, and K. Reick, "Power4 system design for high reliability," Micro, IEEE, vol. 22, no. 2, pp. 16--24, Mar 2002.
[8]
D. C. Bossen, "CMOS Soft Errors and Server Design," IEEE 2002 Reliability Physics Tutorial Notes, Reliability Fundamentals, vol. 121, pp. 07--1, 2002.
[9]
C. Burrowes, A. P. Mihai, D. Ravelosona, J. V. Kim, C. Chappert, L. Vila, A. Marty, Y. Samson, F. Garcia-Sanchez, L. D. Buda-Prejbeanu, I. Tudosa, E. E. Fullerton, and J. P. Attane, "Non-adiabatic spin-torques in narrow magnetic domain walls," Nat Phys, vol. 6, no. 1, pp. 17--21, 01 2010.
[10]
L. Chen and Z. Zhang, "Memguard: A low cost and energy efficient design to support and enhance memory system reliability," in Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser. ISCA '14. Piscataway, NJ, USA: IEEE Press, 2014, pp. 49--60. {Online}. Available: http://dl.acm.org/citation.cfm?id=2665671.2665683
[11]
M. de Kruijf, S. Nomura, and K. Sankaralingam, "Relax: An architectural framework for software recovery of hardware faults," in Proceedings of the 37th Annual International Symposium on Computer Architecture, ser. ISCA '10. New York, NY, USA: ACM, 2010, pp. 497--508. {Online}. Available: http://doi.acm.org/10.1145/1815961.1816026
[12]
X. Dong, C. Xu, Y. Xie, and N. Jouppi, "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 31, no. 7, pp. 994--1007, July 2012.
[13]
S. Feng, S. Gupta, A. Ansari, S. A. Mahlke, and D. I. August, "Encore: Low-cost, fine-grained transient fault recovery," in Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-44. New York, NY, USA: ACM, 2011, pp. 398--409. {Online}. Available: http://doi.acm.org/10.1145/2155620.2155667
[14]
M. Hayashi, "Current driven dynamics of magnetic domain walls in permalloy nanowires," Ph.D. dissertation, Stanford University, 2006.
[15]
R. Huang and G. E. Suh, "Ivec: Off-chip memory integrity protection for both security and reliability," in Proceedings of the 37th Annual International Symposium on Computer Architecture, ser. ISCA '10. New York, NY, USA: ACM, 2010, pp. 395--406. {Online}. Available: http://doi.acm.org/10.1145/1815961.1816015
[16]
A. Iyengar and S. Ghosh, "Modeling and analysis of domain wall dynamics for robust and low-power embedded memory," in Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference. ACM, 2014, pp. 1--6.
[17]
H. Jeon and M. Annavaram, "Warped-dmr: Light-weight error detection for gpgpu," in Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on, Dec 2012, pp. 37--47.
[18]
X. Jian and R. Kumar, "Adaptive reliability chipkill correct (arcc)," in High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, Feb 2013, pp. 270--281.
[19]
R. Kessler, "The alpha 21264 microprocessor," Micro, IEEE, vol. 19, no. 2, pp. 24--36, Mar 1999.
[20]
H. Lee, P. Chen, T. Y. Wu, Y. Chen, C. Wang, P. Tzeng, C. H. Lin, F. Chen, C. Lien, and M. J. Tsai, "Low power and high speed bipolar switching with a thin reactive ti buffer layer in robust hfo2 based rram," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, Dec 2008, pp. 1--4.
[21]
M. Manoochehri, M. Annavaram, and M. Dubois, "Cppc: Correctable parity protected cache," in Proceedings of the 38th Annual International Symposium on Computer Architecture, ser. ISCA '11. New York, NY, USA: ACM, 2011, pp. 223--234. {Online}. Available: http://doi.acm.org/10.1145/2000064.2000091
[22]
C. McNairy and D. Soltis, "Itanium 2 processor microarchitecture," Micro, IEEE, vol. 23, no. 2, pp. 44--55, March 2003.
[23]
I. M. Miron, T. Moore, H. Szambolics, L. D. Buda-Prejbeanu, S. Auffret, B. Rodmacq, S. Pizzini, J. Vogel, M. Bonfim, A. Schuhl, and G. Gaudin, "Fast current-induced domain-wall motion controlled by the rashba effect," Nat Mater, vol. 10, no. 6, pp. 419--423, 06 2011.
[24]
A. Mishra, X. Dong, G. Sun, Y. Xie, N. Vijaykrishnan, and C. Das, "Architecting on-chip interconnects for stacked 3d stt-ram caches in cmps," in Computer Architecture (ISCA), 2011 38th Annual International Symposium on, June 2011, pp. 69--80.
[25]
S. Mukherjee, J. Emer, and S. Reinhardt, "The soft error problem: an architectural perspective," in High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on, Feb 2005, pp. 243--247.
[26]
S. S. Parkin, M. Hayashi, and L. Thomas, "Magnetic domain-wall racetrack memory," Science, vol. 320, no. 5873, pp. 190--194, 2008.
[27]
M. K. Qureshi, "Pay-as-you-go: Low-overhead hard-error correction for phase change memories," in Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-44. New York, NY, USA: ACM, 2011, pp. 318--328. {Online}. Available: http://doi.acm.org/10.1145/2155620.2155658
[28]
A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S.-L. Lu, V. De, and M. Khellah, "Pvt-and-aging adaptive wordline boosting for 8t sram power reduction," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, Feb 2010, pp. 352--353.
[29]
W. Ryan and S. Lin, Channel Codes: Classical and Modern. Cambridge University Press, 2009. {Online}. Available: http://books.google.com/books?id=0gwqxBU\_t-QC
[30]
S. K. Sastry Hari, M.-L. Li, P. Ramachandran, B. Choi, and S. V. Adve, "mswat: Low-cost hardware fault detection and diagnosis for multicore systems," in Proceedings of the 42Nd Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO 42. New York, NY, USA: ACM, 2009, pp. 122--132. {Online}. Available: http://doi.acm.org/10.1145/1669112.1669129
[31]
Y. Sazeides, E. Özer, D. Kershaw, P. Nikolaou, M. Kleanthous, and J. Abella, "Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes," in Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-46. New York, NY, USA: ACM, 2013, pp. 160--171. {Online}. Available: http://doi.acm.org/10.1145/2540708.2540723
[32]
S. Schechter, G. H. Loh, K. Straus, and D. Burger, "Use ecp, not ecc, for hard failures in resistive memories," in Proceedings of the 37th Annual International Symposium on Computer Architecture, ser. ISCA '10. New York, NY, USA: ACM, 2010, pp. 141--152. {Online}. Available: http://doi.acm.org/10.1145/1815961.1815980
[33]
N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H.-H. S. Lee, "Safer: Stuck-at-fault error recovery for memories," in Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO '43. Washington, DC, USA: IEEE Computer Society, 2010, pp. 115--124. {Online}. Available: http://dx.doi.org/10.1109/MICRO.2010.46
[34]
N. H. Seong, S. Yeo, and H.-H. S. Lee, "Tri-level-cell phase change memory: Toward an efficient and reliable memory system," in Proceedings of the 40th Annual International Symposium on Computer Architecture, ser. ISCA '13. New York, NY, USA: ACM, 2013, pp. 440--451. {Online}. Available: http://doi.acm.org/10.1145/2485922.2485960
[35]
S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, "A 4mb embedded slc resistive-ram macro with 7.2ns read-write random-access time and 160ns mlc-access capability," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, Feb 2011, pp. 200--202.
[36]
J. Sim, G. H. Loh, V. Sridharan, and M. O'Connor, "Resilient die-stacked dram caches," in Proceedings of the 40th Annual International Symposium on Computer Architecture, ser. ISCA '13. New York, NY, USA: ACM, 2013, pp. 416--427. {Online}. Available: http://doi.acm.org/10.1145/2485922.2485958
[37]
C. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. Stan, "Relaxing non-volatility for fast and energy-efficient stt-ram caches," in High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, Feb 2011, pp. 50--61.
[38]
G. Sun, C. Xu, and Y. Xie, "Modeling and design exploration of fbdram as on-chip memory," in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, March 2012, pp. 1507--1512.
[39]
Z. Sun, W. Wu, and H. Li, "Cross-layer racetrack memory design for ultra high density and low power consumption," in Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE, May 2013, pp. 1--6.
[40]
S. Tang, A. Keshavarzi, D. Somasekhar, F. Paillet, M. Khellah, Y. Ye, S. Lu, and V. De, "Floating-body dynamic random access memory with purge line," May 11 2006, uS Patent App. 11/289,621. {Online}. Available: http://www.google.com/patents/US20060098482
[41]
A. N. Udipi, N. Muralimanohar, R. Balsubramonian, A. Davis, and N. P. Jouppi, "Lot-ecc: Localized and tiered reliability mechanisms for commodity memory systems," in Proceedings of the 39th Annual International Symposium on Computer Architecture, ser. ISCA '12. Washington, DC, USA: IEEE Computer Society, 2012, pp. 285--296. {Online}. Available: http://dl.acm.org/citation.cfm?id=2337159.2337192
[42]
G. Upasani, X. Vera, and A. González, "Avoiding core's due & sdc via acoustic wave detectors and tailored error containment and recovery," in Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser. ISCA '14. Piscataway, NJ, USA: IEEE Press, 2014, pp. 37--48. {Online}. Available: http://dl.acm.org/citation.cfm?id=2665671.2665682
[43]
R. Venkatesan, S. Ramasubramanian, S. Venkataramani, K. Roy, and A. Raghunathan, "Stag: Spintronic-tape architecture for gpgpu cache hierarchies," in Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, June 2014, pp. 253--264.
[44]
R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, "Tapecache: A high density, energy efficient cache based on domain wall memory," in Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ser. ISLPED '12. New York, NY, USA: ACM, 2012, pp. 185--190.
[45]
Z. Wang, D. Jimenez, C. Xu, G. Sun, and Y. Xie, "Adaptive placement and migration policy for an stt-ram-based hybrid cache," in High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, Feb 2014, pp. 13--24.
[46]
C. Zhang, G. Sun, W. Zhang, F. Mi, H. Li, and W. Zhao, "Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power," in Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific. IEEE, 2015, pp. 100--105.
[47]
Y. Zhang, W. Zhao, D. Ravelosona, J.-O. Klein, J. Kim, and C. Chappert, "Perpendicular-magnetic-anisotropy cofeb racetrack memory," Journal of Applied Physics, vol. 111, no. 9, pp. 093 925--093 925--5, May 2012.
[48]
W. Zhao, Y. Zhang, H.-P. Trinh, J.-O. Klein, C. Chappert, R. Mantovan, A. Lamperti, R. Cowburn, T. Trypiniotis, M. Klaui, J. Heinen, B. Ocker, and D. Ravelosona, "Magnetic domain-wall racetrack memory for high density and fast data storage," in Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on, Oct 2012, pp. 1--4.

Cited By

View all
  • (2025)Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs PerformanceEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-78377-7_16(230-245)Online publication date: 28-Jan-2025
  • (2024)SPIMulator: A Spintronic Processing-in-memory Simulator for RacetracksACM Transactions on Embedded Computing Systems10.1145/364511223:6(1-27)Online publication date: 11-Sep-2024
  • (2024)Enhanced Positional SECDED: Achieving Maximal Double-Error Correction in Racetrack MemoriesIEEE Transactions on Magnetics10.1109/TMAG.2024.335169560:3(1-10)Online publication date: Mar-2024
  • Show More Cited By

Index Terms

  1. Hi-fi playback: tolerating position errors in shift operations of racetrack memory

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture
      June 2015
      768 pages
      ISBN:9781450334020
      DOI:10.1145/2749469
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 13 June 2015

      Permissions

      Request permissions for this article.

      Check for updates

      Qualifiers

      • Research-article

      Funding Sources

      Conference

      ISCA '15
      Sponsor:

      Acceptance Rates

      Overall Acceptance Rate 543 of 3,203 submissions, 17%

      Upcoming Conference

      ISCA '25

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)26
      • Downloads (Last 6 weeks)2
      Reflects downloads up to 25 Feb 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2025)Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs PerformanceEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-78377-7_16(230-245)Online publication date: 28-Jan-2025
      • (2024)SPIMulator: A Spintronic Processing-in-memory Simulator for RacetracksACM Transactions on Embedded Computing Systems10.1145/364511223:6(1-27)Online publication date: 11-Sep-2024
      • (2024)Enhanced Positional SECDED: Achieving Maximal Double-Error Correction in Racetrack MemoriesIEEE Transactions on Magnetics10.1109/TMAG.2024.335169560:3(1-10)Online publication date: Mar-2024
      • (2024)Hierarchical Interleaving and Chained Recovery Schemes of LDPC Codes for Noisy Insertion and Deletion ChannelsIEEE Access10.1109/ACCESS.2024.345460312(125384-125397)Online publication date: 2024
      • (2023)A Multi-Domain Magneto Tunnel Junction for Racetrack Nanowire StripsIEEE Transactions on Nanotechnology10.1109/TNANO.2023.329892022(581-583)Online publication date: 2023
      • (2023)Symbol-Level Detection With Matched Non-Binary LDPC Codes for Position Errors in Racetrack MemoriesIEEE Transactions on Magnetics10.1109/TMAG.2022.321493259:2(1-9)Online publication date: Feb-2023
      • (2023)Correcting Multiple Deletions and Insertions in Racetrack MemoryIEEE Transactions on Information Theory10.1109/TIT.2023.327976669:9(5619-5639)Online publication date: Sep-2023
      • (2023)DownShift: Tuning Shift Reduction With Reliability for Racetrack MemoriesIEEE Transactions on Computers10.1109/TC.2023.325750972:9(2585-2599)Online publication date: 1-Sep-2023
      • (2023) ROLLED: R acetrack Memory O ptimized L inear L ayout and E fficient D ecomposition of Decision Trees IEEE Transactions on Computers10.1109/TC.2022.319709472:5(1488-1502)Online publication date: 1-May-2023
      • (2023)Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETTIEEE Transactions on Computers10.1109/TC.2022.318820672:4(1095-1109)Online publication date: 1-Apr-2023
      • Show More Cited By

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media