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Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8

Published: 13 June 2015 Publication History

Abstract

Transactional Memory (TM) is a new programming paradigm for both simple concurrent programming and high concurrent performance. Hardware Transactional Memory (HTM) is hardware support for TM-based programming. It has lower overhead than software transactional memory (STM), which is a software-based implementation of TM. There are now four commercial systems, IBM Blue Gene/Q, IBM zEnterprise EC12, Intel Core, and IBM POWER8, offering HTM. Our work is the first to compare the performance of these four HTM systems. We measured the STAMP benchmarks, the most widely used TM benchmarks. We also evaluated the specific features of each HTM system. Our experimental results show that: (1) there is no single HTM system that is more scalable than the others in all of the benchmarks, (2) there are measurable performance differences among the HTM systems in some benchmarks, and (3) each HTM system has its own implementation characteristics that limit its scalability.

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  1. Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8

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      cover image ACM Conferences
      ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture
      June 2015
      768 pages
      ISBN:9781450334020
      DOI:10.1145/2749469
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      Published: 13 June 2015

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      • (2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
      • (2023)Flexible scheduling of transactional memory on treesTheoretical Computer Science10.1016/j.tcs.2023.114184(114184)Online publication date: Sep-2023
      • (2022)Using Barrier Elision to Improve Transactional Code GenerationACM Transactions on Architecture and Code Optimization10.1145/353331819:3(1-23)Online publication date: 6-Jul-2022
      • (2022)Cape: compiler-aided program transformation for HTM-based cache side-channel defenseProceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction10.1145/3497776.3517778(181-193)Online publication date: 19-Mar-2022
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      • (2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
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