research-article

LaZy superscalar

Authors:

Görkem Aşılıoğlu,

Soner ÖnderAuthors Info & Claims

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

Pages 260 - 271

https://doi.org/10.1145/2749469.2750409

Published: 13 June 2015 Publication History

Abstract

LaZy Superscalar is a processor architecture which delays the execution of fetched instructions until their results are needed by other instructions. This approach eliminates dead instructions and provides the necessary means to fuse dependent instructions across multiple control dependencies by explicitly tracking control and data dependencies through a matrix based scheduler. We present this novel redesign of scheduling, recovery and commit mechanisms and evaluate the performance of the proposed architecture. Our simulations using Spec 2006 benchmark suite indicate that LaZy Superscalar can achieve significant speed-ups while providing respectable power savings compared to a conventional superscalar processor.

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Cited By

Brandalero MBeck A(2017)A mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streamsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130724(1472-1477)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130724
Gobieski GNagi ASerafin NIsgenc MBeckmann NLucia B(2019)MANICProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358277(670-684)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358277

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cover image ACM Conferences

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

June 2015

768 pages

ISBN:9781450334020

DOI:10.1145/2749469

General Chair:
Debbie Marr
Intel
,
Program Chair:
David Albonesi
Cornell

ACM SIGARCH Computer Architecture News Volume 43, Issue 3S
ISCA'15
June 2015
745 pages
ISSN:0163-5964
DOI:10.1145/2872887
Editor:
Doug DeGroot
acm dot org
Issue’s Table of Contents

Copyright © 2015 ACM.

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Publication History

Published: 13 June 2015

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ISCA '15: The 42nd Annual International Symposium on Computer Architecture

June 13 - 17, 2015

Oregon, Portland

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Brandalero MBeck A(2017)A mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streamsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130724(1472-1477)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130724
Gobieski GNagi ASerafin NIsgenc MBeckmann NLucia B(2019)MANICProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358277(670-684)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358277

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