Abstract
For hard real-time systems, timeliness of operations has to be guaranteed. Static timing analysis is therefore employed to compute upper bounds on the execution times of a program. Analysis results at high precision are required to avoid over-provisioning of resources. For current processors, timing analysis is a complex task mainly due to interdependencies of the processors' features that affect the overall timing behaviour. To still obtain tight bounds, state-of-the-art approaches collect detailed information about these interdependencies by exploring the state space of the system as a whole.
Modern systems, such as multi-core processors, introduce even more timing dependencies -- e.g. due to interference on shared resources between functionally independent programs running on different cores. This will eventually render the above, non-compositional, approach infeasible in terms of analysis runtime and memory consumption. Therefore, recent analysis approaches often assume a certain independence of system components -- referred to as timing compositionality.
We aim at a formal definition of timing compositionality as it was previously only introduced informally. How to achieve timing compositionality in general is an unsolved question. We highlight challenges and summarise open problems that arise in the context of compositional analyses.
- R. Wilhelm et al., "The worst-case execution time problem---overview of methods and survey of tools," ACM Transactions on Embedded Computing Systems (TECS), vol. 7, no. 3, 2008. Google ScholarDigital Library
- R. Heckmann et al., "The influence of processor architecture on the design and the results of WCET tools," Proceedings of the IEEE, vol. 91, no. 7, pp. 1038--1054, July 2003.Google ScholarCross Ref
- M. Alt et al., "Cache behavior prediction by abstract interpretation," in Proceedings of SAS'96, Static Analysis Symposium, ser. LNCS, vol. 1145. Springer Verlag, 1996. Google ScholarDigital Library
- L. Tan, "The worst case execution time tool challenge 2006: The external test," in Proceedings of the 2nd International Symposium on Leveraging Applications of Formal Methods), November 2006. Google ScholarDigital Library
- A. Abel et al., "Impact of resource sharing on performance and performance prediction: A survey," in CONCUR, August 2013. Google ScholarDigital Library
- A. Schranzhofer et al., "Timing analysis for TDMA arbitration in resource sharing systems," in RTAS, April 2010, pp. 215--224. Google ScholarDigital Library
- A. Schranzhofer et al., "Timing analysis for resource access interference on adaptive resource arbiters," in RTAS, April 2011, pp. 213--222. Google ScholarDigital Library
- S. Altmeyer et al., "Cache related pre-emption aware response time analysis for fixed priority pre-emptive systems," in Proceedings of the 32nd IEEE Real-Time Systems Symposium, December 2011, pp. 261--271. Google ScholarDigital Library
- R. Wilhelm et al., "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 28, no. 7, pp. 966--978, July 2009. Google ScholarDigital Library
- S. Altmeyer et al., "Resilience analysis: Tightening the CRPD bound for set-associative caches," in Proceedings of the ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems. ACM, April 2010, pp. 153--162. Google ScholarDigital Library
- P. Atanassov and P. Puschner, "Impact of DRAM refresh on the execution time of real-time tasks," in Proceedings of the IEEE International Workshop on Application of Reliable Computing and Communication, December 2001, pp. 29--34.Google Scholar
- B. Akesson et al., Multiprocessor System-on-Chip: Hardware Design and Tool Integration. Springer, November 2010, ch. 2, pp. 25--56.Google Scholar
- K. Goossens et al., "Virtual execution platforms for mixed-time-criticality applications: the CompSOC architecture and design flow," in Proceedings of the 5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, December 2012, pp. 23--30.Google Scholar
- J. Reineke and R. Sen, "Sound and efficient WCET analysis in the presence of timing anomalies," in Proceedings of 9th International Workshop on Worst-Case Execution Time (WCET) Analysis, June 2009.Google Scholar
- J. Reineke et al., "A definition and classification of timing anomalies," in Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis, July 2006.Google Scholar
- S. Schliecker and R. Ernst, "Real-time performance analysis of multiprocessor systems with shared memory," ACM Trans. Embed. Comput. Syst., vol. 10, no. 2, pp. 22:1--22:27, January 2011. Google ScholarDigital Library
- I. Liu, J. Reineke, and E. A. Lee, "A PRET architecture supporting concurrent programs with composable timing properties," in ASILOMAR. IEEE, 2010, pp. 2111--2115.Google Scholar
- P. Puschner, R. Kirner, and R. G. Pettit, "Towards composable timing for real-time programs," in Software Technologies for Future Dependable Distributed Systems. IEEE, 2009, pp. 1--5. Google ScholarDigital Library
- B. C. Lee et al., "CPR: Composable performance regression for scalable multiprocessor models," in Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO 41. IEEE Computer Society, 2008, pp. 270--281. Google ScholarDigital Library
Index Terms
- Towards compositionality in execution time analysis: definition and challenges
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