research-article

DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors

Authors:

Sanghamitra Roy,

Koushik ChakrabortyAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1

Article No.: 3, Pages 1 - 21

https://doi.org/10.1145/2755558

Published: 02 December 2015 Publication History

Abstract

In this article, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real-world applications. To effectively exploit these delay variations, we propose dynamically adaptable resilient pipeline (DARP)—a series of runtime techniques to boost power-performance efficiency and fault tolerance in a pipelined microprocessor. DARP employs early error prediction to avoid a major portion of the timing errors. We combine DARP with the state-of-art topologically homogeneous and power-performance heterogeneous (THPH) architecture to build up a new frontier for the energy efficiency of multicore processors (DARP-MP). Using a rigorous circuit-architectural infrastructure, we demonstrate that DARP substantially improves the multicore processor performance (9.4--20%) and energy efficiency (10--28.6%) compared to state-of-the-art techniques. The energy-efficiency improvements of DARP-MP are 42% and 49.9% compared against the original THPH and another state-of-art multicore power management scheme, respectively.

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Cited By

Bal ARoy SChakraborty K(2018)Trident: Comprehensive Choke Error Mitigation in NTC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286395426:11(2195-2204)Online publication date: Nov-2018
https://doi.org/10.1109/TVLSI.2018.2863954
Rohbani NEbrahimi MMiremadi STahoori M(2017)Bias Temperature Instability Mitigation via Adaptive Cache Size ManagementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.260657925:3(1012-1022)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2606579

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 1

November 2015

464 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2852253

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

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Copyright © 2015 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 02 December 2015

Accepted: 01 April 2015

Revised: 01 March 2015

Received: 01 October 2014

Published in TODAES Volume 21, Issue 1

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Cited By

Bal ARoy SChakraborty K(2018)Trident: Comprehensive Choke Error Mitigation in NTC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286395426:11(2195-2204)Online publication date: Nov-2018
https://doi.org/10.1109/TVLSI.2018.2863954
Rohbani NEbrahimi MMiremadi STahoori M(2017)Bias Temperature Instability Mitigation via Adaptive Cache Size ManagementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.260657925:3(1012-1022)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2606579

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