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Poster: An Efficient Low Power & High Performance in MPSOC

Published: 10 August 2015 Publication History

Abstract

Multiprocessor system-on-chip (MPSoC) architectures have risen as a prevalent answer to the ever-increasing performance & reduce the power consumption requirements, that are customized to a specific application have the potential to achieve very high performance, while additionally obliging low power consumption. The power consumed and performance of the system mainly depend on the memory and communication medium of processors. There are some issues involved in memory and communication of processors. In this paper we try to avoid those issues and show two separate techniques to increase performance and reduce the power consumption. The first technique is Scratch Pad Memory (SPM) Replacement rather than cache replacement, second technique is Network on Chip (NOC) rather than Advanced Microcontroller Bus Architecture (AMBA) communication medium between processors.

References

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Shaily Mittal and Nitin, "Replacement Policies for Scratch Pad Memory in Embedded Systems," TENCON, pp. 159--163, 2011.
[2]
Shaily Mittal and Nitin, "A New Efficient Replacement Policy for Scratch Pad Memory," 5th International Conference on Computational Intelligence and Communication Networks, pp. 432--435, 2013.
[3]
Sourav Roy, "H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors," 22nd International Conference on VLSI Design, pp. 553--558, 2013.
[4]
George Nikiforos, George Kalokairinos and Vassilis Papaefstathiou, "A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability," 6th HiPEAC Industrial Workshop, Palaiseau, France, Nov, pp. 1--4, 2008.
[5]
Javed Absar and Francky Catthoor, "Deciding Between Scratch-Pad and Cache: An Embedded System Design Problem, " ACM Transactions on Design Automation of Electronic Systems, 2006.
[6]
Huaxi Gul, Kwai Hung Mo, Jiang Xu and Wei Zhang, "A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip," IEEE Computer Society Annual Symposium on VLSI, pp. 19--25, 2009.
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Huaxi Gu, Jiang Xu and Wei Zhang," A Low-Power Fat Tree-based Optical Network-on-Chip for Multiprocessor System-on-Chip" DATE, 2009.
[8]
Bruce Mathewson, "The Evolution of SOC Interconnect and How NOC Fits Within It," DAC, pp. 312--313, 2010.
[9]
Holger Michel, et, "AMBA to SoCWire Network on Chip Bridge as a Backbone for a Dynamic Reconfigurable Processing Unit," NASA/ESA Conference on adaptive hardware and systems, pp. 227--232, 2009.
[10]
Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon and Sunghyun Park, "SCORPIO: A 36-Core Research Chip Demonstrating Snoopy Coherence on a Scalable Mesh NoC with In-Network Ordering," IEEE ISCA, 2014.

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  1. Poster: An Efficient Low Power & High Performance in MPSOC

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      cover image ACM Other conferences
      WCI '15: Proceedings of the Third International Symposium on Women in Computing and Informatics
      August 2015
      763 pages
      ISBN:9781450333610
      DOI:10.1145/2791405
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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 10 August 2015

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      Author Tags

      1. Hardware/Software codesign
      2. MPSOC
      3. NOC
      4. SPM

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      WCI '15

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      WCI '15 Paper Acceptance Rate 98 of 452 submissions, 22%;
      Overall Acceptance Rate 98 of 452 submissions, 22%

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