A. G. Silva-Filho
ABSTRACT
This paper presents an improved differential evolution (DE) algorithm for multi-objective optimization in the discrete domain, applied to a cache memory hierarchy exploration problem, aiming to reduce the energy consumption and to increase the performance to process an embedded application. The architecture exploration is based on cache parameters adjustments and the memory hierarchy is composed of three levels of cache memory. A model of LPDDR2 memory (Low Power DDR2) was adopted to simulate the main memory and a recent cache memory model based on 32 nm transistor technology was used. In these experiments, the proposed algorithm was applied to nine different applications from the MiBench and the MediaBenchII suites. Furthermore, the performance of the proposed strategy was compared with those of SPEA2 and NSGAII optimization mechanisms. The metrics selected to compare the quality of the Pareto front found for each of those algorithms were the hypervolume and the generational distance. The results show that the proposed strategy based on DE optimization algorithm applied to memory hierarchy exploration problem obtained better results for both indicators, achieving improvements in 100% and 78% of cases in both metrics mentioned respectively.
- F. Cordeiro, A. Silva-Filho, C. Araujo, M. Gomes, E. Barros, M. Lima, An environment for energy consumption analysis of cache memories in soc platforms. In (SPL 2010), 2010, pp.35--40.Google Scholar
- S. Segars. Low power design techniques for microprocessors. In Proceedings of International Solid-State Circuits Conference, 2001.Google Scholar
- Zhang, C., Vahid, F. A self-tuning cache architecture for embedded systems. In DATE Conference in Europe, 2004. Google ScholarDigital Library
- Givargis, T., Vahid, F. Platune: a tuning framework for system-ona- chip platforms. Transactions on Computer Aided Design, Nov. 2002. Google ScholarDigital Library
- Palesi, M., Givargis, T. Multi-objective design space exploration using genetic algorithms. Internacional Wordshop on Hardware/Software Codesign, May 2002. Google ScholarDigital Library
- A. Gordon-Ross, F. Vahid, N. Dutt. Automatic Tuning of Two-Level Caches to Embedded Aplications. Design Automation & Test in Europe, Feb. 2004, pp.208--213. Google ScholarDigital Library
- Zhang, C., Vahid, F., Cache configuration exploration on prototyping platforms. 14th IEEE Interational Workshop on Rapid System Prototyping, Jun. 2003. Google ScholarDigital Library
- A. G. Silva-Filho, M. E. Lima, P. S. Nascimento, R. Eskinazi. An Energy-Aware Exploration Approach Based on Open Software Enviroment, IESS, July 2005, pp.97--102.Google Scholar
- A. G. Silva-Filho, F. R. Cordeiro, R. E. Sant'Anna and M. E. Lima. Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance, PATMOS, 2006, pp.75--83. Google ScholarDigital Library
- A. G. Silva-Filho, C. J. A. Bastos-Filho, R. M. F. Lima, D. M. A Falcão, F. R. Cordeiro and M. P. Lima. An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance, SBAC-PAD, 2007, pp.177--184.Google Scholar
- Min Huang; Mehalel, M.; Arvapalli, R.; Songnian He. An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family, (CICC), 2012 IEEE, Sept. 2012, pp.1,4, 9--12.Google Scholar
- Barth, J.; Plass, D.; Nelson, E.; Hwang, C.; et al.. A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache, IEEE Journal of Solid-State Circuits, Vol.46, No.1, Jan. 2011, pp.64, 75.Google ScholarCross Ref
- S. Rusu, S. Tam, H. Muljono, J. Stinson, et al., "A 45 nm 8-core enterprise XEON processor," IEEE J. Solid-State Circuits, vol. 45, pp. 7--14, Jan. 2010.Google ScholarCross Ref
- Jinuk Luke Shin; Golla, R., et al. The Next Generation 64b SPARC Core in a T4 SoC Processor, IEEE Journal of Solid-State Circuits, Vol.48, No.1, Jan. 2013, pp.82, 90.Google ScholarCross Ref
- Freescale Semiconductor. MPC7450 RISC Microprocessor Family Reference Manual, MPC7450UM, Rev. 5, 2005.Google Scholar
- Mingming Zhang; Shuguang Zhao; Xu Wang. Multi-objective evolutionary algorithm based on adaptive discrete Differential Evolution, CEC '09, May 2009, pp.614,621, 18--21. Google ScholarDigital Library
- Chengfu Sun. An improved differential evolution and novel crowding distance metric for multi-objective optimization. (KAM 2010), Oct. 2010, pp.265, 268, 20--21.Google Scholar
- M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown, Mibench: A free, commercially representative embedded benchmark suite. In WWC-4, 2001, pp.3--14. Google ScholarDigital Library
- Jason E. Fritts, Frederick W. Steiling, Joseph A. Tucek. MediaBench II video: expediting the next generation of video systems research. Proc. SPIE 5683, 79 Mar. 2005.Google Scholar
- D. Burger, T. M. Austin, The simplescalar tool set, version 2.0, SIGARCH Comput. Archit. News 25 (3) (1997) 13--25. Google ScholarDigital Library
- Muralimanohar, N., Balasubramonian, R., and Jouppi, N. P. CACTI 6.0. Hewlett Packard Labs, 2009.Google Scholar
- Micron. DDR2 memory power calculator, http://download.micron.com/downloads/misc/ddr2 power calc web.xls. Acessed: 10 April 2013.Google Scholar
Index Terms
- Differential Evolution to Reduce Energy Consumption in Three-Level Memory Hierarchy
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