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Evaluating Geometric Aspects of Non-Series-Parallel Cells

Published: 31 August 2015 Publication History

Abstract

Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel cells, providing useful methods to estimate area and wirelength. These methods can also be applied in series-parallel topologies. The experiments performed in this paper show an effectively optimization on non-series-parallel layouts.

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Cited By

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  • (2018)Area-Aware Design of Static CMOS Complex Gates2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2018.8585570(282-286)Online publication date: Jun-2018
  • (2017)Transistor placement strategies for non-series-parallel cells2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8052975(523-526)Online publication date: Aug-2017
  • (2017)Post-processing of supergate networks aiming cell layout optimization2017 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2017.8050570(1-4)Online publication date: May-2017
  • Show More Cited By

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      cover image ACM Conferences
      SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design
      August 2015
      279 pages
      ISBN:9781450337632
      DOI:10.1145/2800986
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 31 August 2015

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      Author Tags

      1. Placement
      2. automatic layout generation
      3. non-series-parallel networks
      4. physical synthesis
      5. routing

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      SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design
      August 31 - September 4, 2015
      Salvador, Brazil

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      SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;
      Overall Acceptance Rate 133 of 347 submissions, 38%

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      Cited By

      View all
      • (2018)Area-Aware Design of Static CMOS Complex Gates2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2018.8585570(282-286)Online publication date: Jun-2018
      • (2017)Transistor placement strategies for non-series-parallel cells2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8052975(523-526)Online publication date: Aug-2017
      • (2017)Post-processing of supergate networks aiming cell layout optimization2017 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2017.8050570(1-4)Online publication date: May-2017
      • (2017)A post-processing methodology to improve the automatic design of CMOS gates at layout-level2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2017.8292073(42-45)Online publication date: Dec-2017
      • (2016)Physical design of supergate cells aiming geometrical optimizations2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2016.7870091(1-4)Online publication date: Oct-2016

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