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IPNoSys II: A New Architecture for IPNoSys Programming Model

Published: 31 August 2015 Publication History

Abstract

The quest for more performance frequently finds some interesting answers in unconventional computing. IPNoSys is a parallel processing platform for packet-based applications. Its hardware architecture is based on network-on-chip (NoC) structure and its applications are executed while the packets are routed through the NoC. This paper presents a new architecture to IPNoSys programming model. IPNoSys II was developed to provide more performance than the original implementation, supporting the same programming model and allowing parallel execution of a larger number of tasks. IPNoSys II was developed in VHDL and prototyped in FPGA board. Experimental results show that the new architecture can reaches performance five times higher than the original one and 19 times faster than a NoC-based MPSoC using SPARC V8 as processors.

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Cited By

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  • (2021)Performance analysis of application-specific instruction-set routers in networks-on-chipProceedings of the 14th International Workshop on Network on Chip Architectures10.1145/3477231.3490426(16-21)Online publication date: 18-Oct-2021
  • (2019)Using SDN Strategies to Improve Resource Management On a NoC2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920321(224-225)Online publication date: Oct-2019
  • (2018)ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCsComputers10.3390/computers70300387:3(38)Online publication date: 27-Jun-2018

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  1. IPNoSys II: A New Architecture for IPNoSys Programming Model

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    cover image ACM Conferences
    SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design
    August 2015
    279 pages
    ISBN:9781450337632
    DOI:10.1145/2800986
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 31 August 2015

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    Author Tags

    1. IPNoSys Programming Model
    2. NoC
    3. Unconventional Architectures

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    SBCCI '15
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    SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design
    August 31 - September 4, 2015
    Salvador, Brazil

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    SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;
    Overall Acceptance Rate 133 of 347 submissions, 38%

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    Cited By

    View all
    • (2021)Performance analysis of application-specific instruction-set routers in networks-on-chipProceedings of the 14th International Workshop on Network on Chip Architectures10.1145/3477231.3490426(16-21)Online publication date: 18-Oct-2021
    • (2019)Using SDN Strategies to Improve Resource Management On a NoC2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920321(224-225)Online publication date: Oct-2019
    • (2018)ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCsComputers10.3390/computers70300387:3(38)Online publication date: 27-Jun-2018

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