Bypassing method for STT-RAM based inclusive last-level cache

Non-volatile memories (NVMs), such as STT-RAM and PCM, have recently become very competitive designs for last-level caches (LLCs). To avoid cache pollution caused by unnecessary write operations, many cache-bypassing methods have been introduced. Among them, SBAC (a statistics-based cache bypassing method for asymmetric-access caches) is the most recent approach for NVMs and shows the lowest cache access latency. However, SBAC only works on non-inclusive caches, so it is not practical with state-of-the-art processors that employ inclusive LLCs. To overcome this limitation, we propose a novel cache scheme, called inclusive bypass tag cache (IBTC) for NVMs. The proposed IBTC with consideration for the characteristics of NVMs is integrated into LLC to maintain coherence of data in the inclusive LLC with a bypass method and the algorithm is introduced to handle the tag information for bypassed blocks with a minimal storage overhead. Experiments show that IBTC cuts down overall energy consumption by 17.4%, and increases the cache hit rate by 5.1%.