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Early-zero 4-phase micro-pipeline controller with protection

Published: 25 June 2015 Publication History

Abstract

A thorough and detailed analysis of an asynchronous 4-phase transfer protocol with early-zero reset is presented. The protocol is implemented by a micro-pipeline controller whose register-fixative (pipeline register) is implemented by dynamic (Edge) flip-flops, writing data by the rising edge of the signal. Based on this analysis two original results are obtained. The first one: the possible time interval for the reset of the micro-pipeline controller is defined. The second one is about the possibility of false switching of the controller. Different variants of logic schemes are commented in relations with the findings of the analysis. Technical requirements which the logical synthesis is based on are defined for both problems. The principle logical circuit of the pipeline controller is presented. It's functioning is explained in details by a timing diagram.

References

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Mohideen, S. K., J. R. Perinbam. Design of Low Power Double Edge Triggered D Flip Flop. Asian Journal of Information Technology, Vol. 5, No 10, ISSN: 1682--3915, pp. 1113--1116, 2006.
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Mohideen, S. K., R. J. Pernbam. An Effective Asynchronous Micropipeline using Double Edge Triggered D Flipflop. International Journal of Applied Engineering Research, ISSN: 0973-4562, Vol.2, No 1, pp. 139--146, 2007.
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Tyanev, D. S. Computer organization. Design. Technical University of Varna. Bulgaria. ISBN: 954-20-0259-9.

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cover image ACM Other conferences
CompSysTech '15: Proceedings of the 16th International Conference on Computer Systems and Technologies
June 2015
411 pages
ISBN:9781450333573
DOI:10.1145/2812428
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • UORB: University of Ruse, Bulgaria
  • Querbie: Querbie
  • TECHUVB: Technical University of Varna, Bulgaria

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 June 2015

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Author Tags

  1. 4-phase protocol
  2. micro-pipeline
  3. signal "completion detection"

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CompSysTech '15
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  • UORB
  • Querbie
  • TECHUVB

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