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Hardware-assisted Memory Tracing on New SoCs Embedding FPGA Fabrics

Published: 07 December 2015 Publication History

Abstract

The FPGA world recently experienced significant changes with the introduction of new Systems-on-Chip (SoCs) embedding high-end microprocessors and programmable logic on the same integrated circuit. The architecture of these SoCs can be exploited to offer an unprecedented level of monitoring of the memory accesses of running software components, a key element of performance, safety and security analysis. This paper presents the hardware / software implementation of such a memory tracing tool on one of these SoCs. It also proposes example applications in the security field and two attacks --- a pass-phrase retrieval and an access control bypass --- to demonstrate the power of hardware-assisted memory tracing.

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Cited By

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  • (2022)Scramblesuit: An effective timing side-channels framework for malware sandbox evasion1Journal of Computer Security10.3233/JCS-22000530:6(851-876)Online publication date: 23-Nov-2022
  • (2021)Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoCJournal of Cryptographic Engineering10.1007/s13389-021-00273-812:2(181-196)Online publication date: 15-Sep-2021
  • (2021)PoW-How: An Enduring Timing Side-Channel to Evade Online Malware SandboxesComputer Security – ESORICS 202110.1007/978-3-030-88418-5_5(86-109)Online publication date: 4-Oct-2021
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Published In

cover image ACM Other conferences
ACSAC '15: Proceedings of the 31st Annual Computer Security Applications Conference
December 2015
489 pages
ISBN:9781450336826
DOI:10.1145/2818000
Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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  • ACSA: Applied Computing Security Assoc

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 December 2015

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Author Tags

  1. Memory tracing
  2. Systems-on-Chip
  3. memory protection

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ACSAC 2015

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Overall Acceptance Rate 104 of 497 submissions, 21%

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Cited By

View all
  • (2022)Scramblesuit: An effective timing side-channels framework for malware sandbox evasion1Journal of Computer Security10.3233/JCS-22000530:6(851-876)Online publication date: 23-Nov-2022
  • (2021)Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoCJournal of Cryptographic Engineering10.1007/s13389-021-00273-812:2(181-196)Online publication date: 15-Sep-2021
  • (2021)PoW-How: An Enduring Timing Side-Channel to Evade Online Malware SandboxesComputer Security – ESORICS 202110.1007/978-3-030-88418-5_5(86-109)Online publication date: 4-Oct-2021
  • (2020)Analyzing memory accesses with modern processorsProceedings of the 16th International Workshop on Data Management on New Hardware10.1145/3399666.3399896(1-9)Online publication date: 15-Jun-2020
  • (2019)Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoCProceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop10.1145/3338508.3359568(3-12)Online publication date: 15-Nov-2019
  • (2017)Compromising FPGA SoCs using malicious hardware blocksProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130644(1122-1127)Online publication date: 27-Mar-2017
  • (2017)Compromising FPGA SoCs using malicious hardware blocksDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927157(1122-1127)Online publication date: Mar-2017
  • (2017)How to Break Secure Boot on FPGA SoCs Through Malicious HardwareCryptographic Hardware and Embedded Systems – CHES 201710.1007/978-3-319-66787-4_21(425-442)Online publication date: 25-Aug-2017

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