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SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype

Published: 05 October 2015 Publication History

Abstract

Stacked DRAM products are now available, and the likelihood of future products combining DRAM stacks with custom logic layers seems high. The near-memory processor in such a system will have to be energy efficient, latency tolerant, and capable of exploiting both high memory-level parallelism and high memory bandwidth. We believe that single-instruction-multiple-thread (SIMT) processors are uniquely suited to this task, and for the purpose of evaluating this claim have produced an FPGA-based prototype.

References

[1]
H. M. C. Consortium et al. Hybrid memory cube specification 1.0, 2013.
[2]
C. Kersey, S. Yalamanchili, H. Kim, N. Nigania, and H. Kim. Harmonica: An fpga-based data parallel soft core. In Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on, pages 171--171. IEEE, 2014.

Cited By

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  • (2016)Integrated Thermal Analysis for Processing In Die-Stacking MemoryProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989093(402-414)Online publication date: 3-Oct-2016
  • (2016)Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications2016 45th International Conference on Parallel Processing Workshops (ICPPW)10.1109/ICPPW.2016.31(115-122)Online publication date: Aug-2016

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MEMSYS '15: Proceedings of the 2015 International Symposium on Memory Systems
October 2015
278 pages
ISBN:9781450336048
DOI:10.1145/2818950
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 October 2015

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MEMSYS '15
MEMSYS '15: International Symposium on Memory Systems
October 5 - 8, 2015
DC, Washington DC, USA

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Cited By

View all
  • (2016)Integrated Thermal Analysis for Processing In Die-Stacking MemoryProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989093(402-414)Online publication date: 3-Oct-2016
  • (2016)Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications2016 45th International Conference on Parallel Processing Workshops (ICPPW)10.1109/ICPPW.2016.31(115-122)Online publication date: Aug-2016

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