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A Data Centric Perspective on Memory Placement

Published: 05 October 2015 Publication History

Abstract

In this paper, we focus on memory in its role as a channel for passing information from one instruction to another; in particular, in conjunction with spatial or dataflow computing architectures, wherein the computing elements are laid out like an assembly plant. We point out the opportunity to dramatically increase effective data access bandwidth by going from a centralized memory array model with a few ports to numerous tiny buffers that can be accessed concurrently. The penalty is loss in access flexibility, but this flexibility is often a by-product of the memory organization rather than a true need. The improvements in hardware reconfiguration speed and resolution, combined with definition of standard buffer queuing and routing capabilities and efforts by tool designers and application developers are likely to extend the applicability of those architectures, offering dramatic power-cost-performance advantages.

References

[1]
Dally, W.J. and Towles, B., 2001. Route packets, not wires: on-chip interconnection networks. Proc. DAC, (Las Vegas, Nevada, USA, June 18--22, 2001).
[2]
Dennis, J.B., 1980. Data Flow Supercomputers. IEEE Computer 13, 11 (Nov. 1980), 48--56.
[3]
OpenSPL Forum. 2015. www.openspl.org
[4]
Pell, O. and Averbukh, V., 2012. Maximum Performance Computing with Dataflow Engines. Computing in Science & Engineering, July--Aug. 2012. DOI=10.1109/MCSE.2012.78.

Cited By

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  • (2019)Reliability Issues in the Parallel Dataflow Computing System2019 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2019.8884439(1-5)Online publication date: Sep-2019

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MEMSYS '15: Proceedings of the 2015 International Symposium on Memory Systems
October 2015
278 pages
ISBN:9781450336048
DOI:10.1145/2818950
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 October 2015

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Author Tags

  1. Spatial computing
  2. data centric
  3. dataflow engine
  4. memory organization

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  • Extended-abstract
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  • Refereed limited

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MEMSYS '15
MEMSYS '15: International Symposium on Memory Systems
October 5 - 8, 2015
DC, Washington DC, USA

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Cited By

View all
  • (2019)Reliability Issues in the Parallel Dataflow Computing System2019 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2019.8884439(1-5)Online publication date: Sep-2019

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