Cited By
View all- del Campo FChow PJacob B(2017)Task replication and control for highly parallel in-memory storesProceedings of the International Symposium on Memory Systems10.1145/3132402.3132428(312-326)Online publication date: 2-Oct-2017
The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-...
Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, designers tried to alleviate this problem by relying on a simple cache hierarchy, or a limited use of special purpose memory modules such as stream ...
Larger last level caches are being considered for bridging the performance gap between the processors and the memory subsystem. It requires much longer simulation time to exercise the whole cache and get accurate evaluation results. In this paper, we ...
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