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WCET analysis for multi-core processors with shared buses and event-driven bus arbitration

Published: 04 November 2015 Publication History

Abstract

Multi-core processors share common hardware resources between several processor cores. As a consequence, a program executed on one processor core may influence the execution time of the programs executed on the concurrent cores. This effect is commonly referred to as shared-resource interference. Worst-case execution time (WCET) analysis for multi-core processors has to take into account the shared-resource interference.
Most existing approaches to WCET analysis for multi-core processors with shared buses and event-driven bus arbitration rely on compositionality. These approaches, however, do not support complex processor core pipelines. The existing approaches that support complex pipelines perform an exhaustive enumeration of possible interleavings of accesses to the shared bus by the different cores. Such an enumeration is infeasible in most cases.
Our approach extends the state of the art in WCET analysis for single-core processors in such a way that it can deal with shared-bus interference. It does not rely on compositionality or enumeration of interleavings. Our approach calculates co-runner-insensitive WCET bounds, that are independent of the programs executed in parallel. Furthermore, it is able to improve those bounds by taking into account the bus access behavior of the concurrent cores and, thus, to calculate co-runner-sensitive WCET bounds.
The implementation of our approach is evaluated for different multi-core processors. Our calculation of co-runner-insensitive WCET bounds is shown to be almost independent of the number of processor cores in terms of runtime and memory consumption. The co-runner-sensitive WCET bounds are up to 12.5% smaller than the co-runner-insensitive ones for a dual-core processor.

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RTNS '15: Proceedings of the 23rd International Conference on Real Time and Networks Systems
November 2015
320 pages
ISBN:9781450335911
DOI:10.1145/2834848
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 04 November 2015

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RTNS '15 Paper Acceptance Rate 31 of 66 submissions, 47%;
Overall Acceptance Rate 119 of 255 submissions, 47%

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  • (2022)CPU Execution Time Analysis based on RISC-V ISA Simulators: A Survey2022 International Conference on Development and Application Systems (DAS)10.1109/DAS54948.2022.9786163(12-18)Online publication date: 26-May-2022
  • (2021)Evaluation and ValidationEmbedded System Design10.1007/978-3-030-60910-8_5(239-293)Online publication date: 26-Jan-2021
  • (2020)Compilation for Real-Time Systems a Decade After PredatorA Journey of Embedded and Cyber-Physical Systems10.1007/978-3-030-47487-4_10(151-169)Online publication date: 31-Jul-2020
  • (2019)Code-Inherent Traffic Shaping for Hard Real-Time SystemsACM Transactions on Embedded Computing Systems10.1145/335821518:5s(1-21)Online publication date: 8-Oct-2019
  • (2019)A Survey of Timing Verification Techniques for Multi-Core Real-Time SystemsACM Computing Surveys10.1145/332321252:3(1-38)Online publication date: 18-Jun-2019
  • (2019)Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules2019 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS46320.2019.00030(233-245)Online publication date: Dec-2019
  • (2018)Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAMProceedings of the 26th International Conference on Real-Time Networks and Systems10.1145/3273905.3273908(148-158)Online publication date: 10-Oct-2018
  • (2016)Enabling Compositionality for Multicore Timing AnalysisProceedings of the 24th International Conference on Real-Time Networks and Systems10.1145/2997465.2997471(299-308)Online publication date: 19-Oct-2016
  • (2016)Combining robotics component-based model-driven development with a model-based performance analysis2016 IEEE International Conference on Simulation, Modeling, and Programming for Autonomous Robots (SIMPAR)10.1109/SIMPAR.2016.7862392(170-176)Online publication date: Dec-2016
  • (2016)A Framework for the Derivation of WCET Analyses for Multi-core Processors2016 28th Euromicro Conference on Real-Time Systems (ECRTS)10.1109/ECRTS.2016.19(141-151)Online publication date: Jul-2016

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