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Black box power estimation for digital signal processors using virtual platforms

Published: 18 January 2016 Publication History

Abstract

Complex many-core architectures are seen as the solution to tackle the computational workloads of the next years. To find the best trade-off between power and performance, different processor architectures have to be considered and evaluated in a thorough and power-aware design space exploration. This is highly facilitated by electronic system level (ESL) using virtual platforms. However, state-of-the-art methods of estimating power consumption require insight into the models of the platform. Or in case no insight is necessary, they are limited to only RISC architectures. The former requirement is in conflict with widely used proprietary models shipped as binary objects, i.e. black boxes.
The methodology in this paper deals with both issues by enabling ESL black box power estimation for digital signal processors (DSP) using semi-automatic calibrated power models. Additionally, a case study reveals a high accuracy with a power estimation error of less than 4% for the Black-Fin 609 DSP on the FinBoard.

References

[1]
Docea Aceplorer. {Online} http://www.doceapower.com/index.php?option=com_content&view=article&id=1&Itemid=102 (accessed 09/2015).
[2]
SystemC. {Online} http://www.accellera.org/downloads/standards/systemc (accessed 09/2015).
[3]
USB-DUXfast: Technical specification. {Online} http://www.linux-usb-daq.co.uk/tech2_duxfast/ (accessed 09/2015).
[4]
FinBoard hardware user guide. {Online} http://finboard.org/documentation/ (accessed 09/2015), 2013.
[5]
ADSP-BF606 607 608 609. {Online} http://www.analog.com/en/products/processors-dsp/blackfin/adsp-bf609.html#product-documentation (accessed 09/2015), 2014.
[6]
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Computer Architecture, 2000. Proceedings of the 27th International Symposium on, June 2000.
[7]
L. Eeckhout and K. D. Bosschere. Early design phase power/performance modeling through statistical simulation. In Proc. 2001 IEEE Intl. Symp. on Performance Analysis of Systems and Software. IEEE, 2001.
[8]
D. Greaves and M. Yasin. TLM POWER3: Power estimation methodology for SystemC TLM 2.0. In Proceedings of the 2012 Forum on specification & Design Languages, Semptember 2012.
[9]
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In Workload Characterization, WWC-4. IEEE CS, 2001.
[10]
W.-T. Hsieh, J.-C. Yeh, S.-C. Lin, H.-C. Liu, and Y.-S. Chen. System power analysis with DVFS on ESL virtual platform. In SOC Conference (SOCC), 2011 IEEE International, 2011.
[11]
M. Jung, C. Weis, P. Bertram, G. Braun, and N. Wehn. Power modelling of 3D-stacked memories with TLM 2.0 based virtual platforms. In Synopsys User Group Conference (SNUG), May 2013.
[12]
S. Kumar Rethinagiri, O. Palomar, J. Arias Moreno, O. Unsal, and A. Cristal. VPPET: Virtual platform power and estimation tool for heterogeneous MPSoC based FPGA platforms. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014.
[13]
J. Laurent, N. Julien, E. Senn, and E. Martin. Functional level power analysis: an efficient approach for modeling the power consumption of complex processors. In Design, Automation and Test in Europe Conference and Exhibition, 2004.
[14]
S. Pasricha, Y.-H. Park, F. Kurdahi, and N. Dutt. System-level power-performance trade-offs in bus matrix communication architecture synthesis. In Hardware/Software Codesign and System Synthesis., 2006.
[15]
S. K. Rethinagiri, O. Palomar, R. Ben Atitallah, S. Niar, O. Unsal, and A. C. Kestelman. System-level power estimation tool for embedded processor based platforms. In Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014.
[16]
S. Schürmans, G. Onnebrink, R. Leupers, G. Ascheid, and X. Chen. ESL power estimation using virtual platforms with black box processor models. In ViPES Workshop 2015.
[17]
S. Schürmans, D. Zhang, D. Auras, R. Leupers, G. Ascheid, X. Chen, and L. Wang. Creation of ESL power models for communication architectures using automatic calibration. In Design Automation Conference (DAC), 2013.
[18]
M. Själander, S. McKee, P. Brauer, D. Engdal, and A. Vajda. An LTE uplink receiver PHY benchmark and subframe-based power management. In Performance Analysis of Systems and Software (ISPASS). IEEE, 2012.
[19]
M. Streubühr, R. Rosales, R. Hasholzner, C. Haubelt, and J. Teich. ESL power and performance estimation for heterogeneous MPSoCs using SystemC. In Specification and Design Languages (FDL), 2011.
[20]
Synopsys virtualizer. {Online} http://www.synopsys.com/prototyping/virtualprototyping/pages/virtualizer.aspx (accessed 09/2015).
[21]
W. Thies, M. Karczmarek, and S. Amarasinghe. StreamIt: A language for streaming applications. In Intl. Conference on Compiler Construction, Grenoble, France, 2002.
[22]
Y. Veller and S. Matalon. Why you should optimize power at the ESL -- Whitepaper, Mentor Graphics. {Online} http://go.mentor.com/cvtq (accessed 09/2015), Aug 2010.
[23]
R. P. Weicker. Dhrystone: A synthetic systems programming benchmark. Comm. ACM, 1984.
[24]
W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. The design and use of Simplepower: A cycle-accurate energy estimation tool. In Proceedings of the 37th Annual Design Automation Conference, 2000.
[25]
Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, and T. Mudge. WiBench: An open source kernel suite for benchmarking wireless systems. In Workload Characterization (IISWC), 2013.

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  • (2023)SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323687(1-8)Online publication date: 28-Oct-2023
  • (2020)PESL: System-Level Estimation of Power-Management Effect on Dynamic Energy ConsumptionElectronics10.3390/electronics90813139:8(1313)Online publication date: 15-Aug-2020
  • (2020)3D Optimisation of Software Application Mappings on Heterogeneous MPSoCsArchitecture of Computing Systems – ARCS 202010.1007/978-3-030-52794-5_5(56-68)Online publication date: 9-Jul-2020
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cover image ACM Other conferences
RAPIDO '16: Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
January 2016
41 pages
ISBN:9781450340724
DOI:10.1145/2852339
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2016

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Author Tags

  1. digital signal processor
  2. electronic system level
  3. power estimation
  4. power model

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RAPIDO '16

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Overall Acceptance Rate 14 of 28 submissions, 50%

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Cited By

View all
  • (2023)SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323687(1-8)Online publication date: 28-Oct-2023
  • (2020)PESL: System-Level Estimation of Power-Management Effect on Dynamic Energy ConsumptionElectronics10.3390/electronics90813139:8(1313)Online publication date: 15-Aug-2020
  • (2020)3D Optimisation of Software Application Mappings on Heterogeneous MPSoCsArchitecture of Computing Systems – ARCS 202010.1007/978-3-030-52794-5_5(56-68)Online publication date: 9-Jul-2020
  • (2018)ESL Black Box Power EstimationProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180667(1-6)Online publication date: 22-Jan-2018
  • (2018)Conclusions and OutlookPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_7(207-211)Online publication date: 15-Dec-2018
  • (2017)DVFS-enabled power-performance trade-off in MPSoC SW application mapping2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2017.8344628(196-202)Online publication date: Jul-2017
  • (2016)Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor ModelACM Transactions on Embedded Computing Systems10.1145/298737516:1(1-26)Online publication date: 13-Oct-2016
  • (2016)Black box ESL power estimation for loosely-timed TLM models2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818374(366-371)Online publication date: Jul-2016

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