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Exploiting mixed SIMD parallelism by reducing data reorganization overhead

Published: 29 February 2016 Publication History

Abstract

Existing loop vectorization techniques can exploit either intra- or inter-iteration SIMD parallelism alone in a code region if one part of the region vectorized for one type of parallelism has data dependences (called mixed-parallelism-inhibiting dependences) on the other part of the region vectorized for the other type of parallelism. In this paper, we consider a class of loops that exhibit both types of parallelism (i.e., mixed SIMD parallelism) in its code regions that contain mixed-parallelism-inhibiting data dependences. We present a new compiler approach for exploiting such mixed SIMD parallelism effectively by reducing the data reorganization overhead incurred when one type of parallelism is switched to the other. Our auto-vectorizer is simple and has been implemented in LLVM (3.5.0). We evaluate it on seven benchmarks with mixed SIMD parallelism selected from SPEC and NAS benchmark suites and demonstrate its performance advantages over the state-of-the-art.

References

[1]
R. Allen and K. Kennedy. Automatic translation of fortran programs to vector form. ACM Trans. Program. Lang. Syst., 9(4):491–542, 1987.
[2]
R. Barik, J. Zhao, and V. Sarkar. Efficient selection of vector instructions using dynamic programming. In MICRO’10, pages 201–212.
[3]
G. Barthe, J. M. Crespo, S. Gulwani, C. Kunz, and M. Marron. From relational verification to simd loop synthesis. In PPoPP ’13, pages 123–134.
[4]
A. E. Eichenberger, P. Wu, and K. O’Brien. Vectorization for SIMD architectures with alignment constraints. In PLDI ’04, pages 82–93.
[5]
Intel. Intel R 64 and IA-32 Architectures Optimization Reference Manual. Number 248966-030. September 2014.
[6]
R. Karrenberg and S. Hack. Whole-function vectorization. In CGO ’11, pages 141–150.
[7]
S. Kim and H. Han. Efficient SIMD code generation for irregular kernels. In PPoPP ’12, pages 55–64.
[8]
M. Kong, R. Veras, K. Stock, F. Franchetti, L.-N. Pouchet, and P. Sadayappan. When polyhedral transformations meet SIMD code generation. In PLDI ’13, pages 127–138.
[9]
S. Larsen and S. Amarasinghe. Exploiting superword level parallelism with multimedia instruction sets. In PLDI ’00, pages 145–156.
[10]
S. Larsen, E. Witchel, and S. P. Amarasinghe. Increasing and detecting memory address congruence. In PACT ’02, pages 18–29.
[11]
J. Liu, Y. Zhang, O. Jang, W. Ding, and M. Kandemir. A compiler framework for extracting superword level parallelism. In PLDI ’12, pages 347–358.
[12]
S. Maleki, Y. Gao, M. J. Garzarán, T. Wong, and D. A. Padua. An evaluation of vectorizing compilers. In PACT ’11, pages 372–382.
[13]
D. Nuzman, I. Rosen, and A. Zaks. Auto-vectorization of interleaved data for SIMD. In PLDI ’06, pages 132–143.
[14]
Y. Park, S. Seo, H. Park, H. K. Cho, and S. Mahlke. SIMD defragmenter: Efficient ILP realization on data-parallel architectures. In ASPLOS XVII, pages 363–374.
[15]
V. Porpodas and T. M. Jones. Throttling automatic vectorization: When less is more. In PACT’15.
[16]
V. Porpodas, A. Magni, and T. M. Jones. PSLP: Padded SLP automatic vectorization. In CGO’15, pages 190–201.
[17]
G. Ren, P. Wu, and D. Padua. Optimizing data permutations for SIMD devices. In PLDI ’06, pages 118–131.
[18]
I. Rosen, D. Nuzman, and A. Zaks. Loop-aware SLP in GCC. In GCC Developers’ Summit’07, pages 131–142.
[19]
J. Shin. Introducing control flow into vectorized code. In PACT ’07, pages 280–291.
[20]
J. Shin, J. Chame, and M. W. Hall. Compiler-controlled caching in superword register files for multimedia extension architectures. In PACT ’02, pages 45–55,.
[21]
J. Shin, M. Hall, and J. Chame. Superword-level parallelism in the presence of control flow. In CGO ’05, pages 165–175,.
[22]
M. H. Sujon, R. C. Whaley, and Q. Yi. Vectorization past dependent branches through speculation. In PACT ’13, pages 353–362.
[23]
K. Trifunovic, D. Nuzman, A. Cohen, A. Zaks, and I. Rosen. Polyhedral-model guided loop-nest auto-vectorization. In PACT ’09, pages 327–337.
[24]
P. Wu, A. E. Eichenberger, A. Wang, and P. Zhao. An integrated simdization framework using virtual vectors. In ICS ’05, pages 169–178.
[25]
H. Zima and B. Chapman. Supercompilers for Parallel and Vector Computers. ACM, 1991.

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    cover image ACM Conferences
    CGO '16: Proceedings of the 2016 International Symposium on Code Generation and Optimization
    February 2016
    283 pages
    ISBN:9781450337786
    DOI:10.1145/2854038
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    Published: 29 February 2016

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    1. Loop vectorization
    2. SLP
    3. data reorganization optimization
    4. mixed SIMD parallelism

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    CGO '16 Paper Acceptance Rate 25 of 108 submissions, 23%;
    Overall Acceptance Rate 312 of 1,061 submissions, 29%

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