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Path Selection for Real-Time Communication on Priority-Aware NoCs

Published: 21 July 2016 Publication History

Abstract

This work investigates selecting paths for communication flows when deploying a hard real-time application on a chip-multiprocessor system. This chip-multiprocessor system uses a priority-aware real-time network-on-chip interconnect between the processors. Given a mapping of the computation tasks onto the chip-multiprocessor, the problem we address in this work is to discover paths the communication flows take such that hard real-time deadlines of flows are met. Furthermore, we must ensure that deadlines are met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a stage-level analysis for real-time communication to determine the impact of a network link being used by a flow, and its effect on other flows sharing the link. The path selection algorithm uses heuristics such as selecting links with least interference, and considering lower-priority flows when dedicating links to paths of higher-priority flows since an optimal one is intractable. The algorithm also considers constraints on the number of virtual channels at each router port in the network. The statistically significant experimental results show an improvement in schedulability by 5% and 12% over existing path selection algorithms such as Minimum Interference Routing and Widest Shortest Path algorithms, respectively. We also present a set-top box case study to further illustrate the benefits of using the proposed algorithm.

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  • (2022)Network topology generation based on eigenvector centrality with real‐time guaranteeConcurrency and Computation: Practice and Experience10.1002/cpe.695535:21Online publication date: 22-Mar-2022

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 21, Issue 3
      Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
      July 2016
      434 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2926747
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 21 July 2016
      Accepted: 01 December 2015
      Revised: 01 October 2015
      Received: 01 March 2015
      Published in TODAES Volume 21, Issue 3

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      Author Tags

      1. Network-on-chip
      2. path selection

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      • (2022)Network topology generation based on eigenvector centrality with real‐time guaranteeConcurrency and Computation: Practice and Experience10.1002/cpe.695535:21Online publication date: 22-Mar-2022

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