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Drive Strength Aware Cell Movement Techniques for Timing Driven Placement

Published: 03 April 2016 Publication History

Abstract

As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design flow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly addresses timing. A timing-driven placement incorporates timing information to remove or alleviate timing violations. In this work, we present an incremental timing-driven placement flow to further optimize timing violations via single-cell movements.For late violations, we developed techniques to reduce the load capacitance on critical nets and to obtain load capacitance balancing using drive strength. For early violations, we present techniques that rely on clock skew optimization, register swap and interconnection increase. Our flow is experimentally evaluated using the ICCAD 2015 Incremental Timing-Driven Contest infrastructure. Experimental results show that our flow can significantly reduce timing violations. On average, for long maximum displacement, the quality of results is improved by 67.8% with late WNS and TNS being improved by 2.31% and 10.84%, respectively, early WNS and TNS improved by 68.92% and 76.42%, respectively and congestion metric ABU improved by 74.9% compared to the 1st place in the contest. The impact on Steiner tree wirelength is less than 2.5%.

References

[1]
R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. Network Flows: Theory, Algorithms, and Applications. Prentice-Hall, Inc., Upper Saddle River, NJ, USA, 1993.
[2]
A. Bock, S. Held, N. Kammerling, and U. Schorr. Local search algorithms for timing-driven placement under arbitrary delay models. In DAC, pages 29:1--29:6. ACM, 2015.
[3]
M. Burstein and M. Youssef. Timing influenced layout design. In DAC, pages 124--130, June 1985.
[4]
W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers. Journal of Applied Physics, 19(1):55--63, Jan. 1948.
[5]
C. Guth, V. Livramento, R. Netto, R. Fonseca, J. L. Güntzel, and L. Santos. Timing-driven placement based on dynamic net-weighting for efficient slack histogram compression. In ISPD, pages 141--148. ACM, 2015.
[6]
S. Held and U. Schorr. Post-routing latch optimization for timing closure. In DAC, pages 7:1--7:6. ACM, 2014.
[7]
M.-C. Kim, J. Hu, J. Li, and N. Viswanathan. Iccad-2015 cad contest in incremental timing-driven placement and benchmark suite. In ICCAD, pages 921--926, Nov 2015.
[8]
M.-C. Kim, J. Huj, and N. Viswanathan. Iccad-2014 cad contest in incremental timing-driven placement and benchmark suite: Special session paper: Cad contest. In ICCAD, pages 361--366, Nov 2014.
[9]
T. Kong. A novel net weighting algorithm for timing-driven placement. In ICCAD, pages 172--176, Nov 2002.
[10]
H. W. Kuhn. The hungarian method for the assignment problem. Naval Research Logistics Quarterly, 2(1--2):83--97, 1955.
[11]
D. Papa, T. Luo, M. Moffitt, C. Sze, Z. Li, G.-J. Nam, C. Alpert, and I. Markov. Rumble: An incremental timing-driven physical-synthesis optimization algorithm. TCAD, 27(12):2156--2168, Dec 2008.
[12]
J. Puget, G. Flach, M. Johann, and R. Reis. Jezz: An effective legalization algorithm forminimum displacement. In SBCCI, Sept 2015.
[13]
R.-S. Tsay and J. Koehl. An analytic net weighting approach for performance optimization in circuit placement. In DAC, pages 620--625, June 1991.
[14]
N. Viswanathan, G.-J. Nam, J. A. Roy, Z. Li, C. J. Alpert, S. Ramji, and C. Chu. Itop: Integrating timing optimization within placement. In ISPD, pages 83--90. ACM, 2010.
[15]
Q. B. Wang, J. Lillis, and S. Sanyal. An lp-based methodology for improved timing-driven placement. In ASP-DAC, volume 2, pages 1139--1143 Vol. 2, Jan 2005.
[16]
C. S. William Swartz. Timing driven placement for large standard cell circuits. In DAC, pages 211--215, 1995.

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  • (2024)Electrostatics-Based Analytical Global Placement for Timing Optimization2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546800(1-6)Online publication date: 25-Mar-2024
  • (2023)IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design StagesACM Transactions on Design Automation of Electronic Systems10.1145/357254628:4(1-23)Online publication date: 17-May-2023
  • (2023)Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay2023 IEEE Silchar Subsection Conference (SILCON)10.1109/SILCON59133.2023.10404446(1-6)Online publication date: 3-Nov-2023
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    cover image ACM Conferences
    ISPD '16: Proceedings of the 2016 on International Symposium on Physical Design
    April 2016
    180 pages
    ISBN:9781450340397
    DOI:10.1145/2872334
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Published: 03 April 2016

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    Author Tags

    1. eda
    2. microelectronics
    3. timing-driven placement
    4. timingclosure

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    April 3 - 6, 2016
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    View all
    • (2024)Electrostatics-Based Analytical Global Placement for Timing Optimization2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546800(1-6)Online publication date: 25-Mar-2024
    • (2023)IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design StagesACM Transactions on Design Automation of Electronic Systems10.1145/357254628:4(1-23)Online publication date: 17-May-2023
    • (2023)Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay2023 IEEE Silchar Subsection Conference (SILCON)10.1109/SILCON59133.2023.10404446(1-6)Online publication date: 3-Nov-2023
    • (2022)An Incremental Placement Flow for Advanced FPGAs With Timing AwarenessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312007041:9(3092-3103)Online publication date: Sep-2022
    • (2020)Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop ClusteringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294200139:10(2835-2848)Online publication date: Oct-2020
    • (2019)An Optimized Cost Flow Algorithm to Spread Cells in Detailed PlacementACM Transactions on Design Automation of Electronic Systems10.1145/331757524:3(1-16)Online publication date: 2-Apr-2019
    • (2019)Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell DelayIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291525427:10(2434-2446)Online publication date: Oct-2019
    • (2019)Impact of Complex Logic Cell Layout on the Single-Event Transient SensitivityIEEE Transactions on Nuclear Science10.1109/TNS.2019.291807766:7(1465-1472)Online publication date: Jul-2019
    • (2019)Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00059(284-289)Online publication date: Jul-2019
    • (2019)Methodology for Congestion Reduction and Timing Closure During Placement2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)10.1109/IEMENTech48150.2019.8981032(1-4)Online publication date: Aug-2019
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