Some Observations on the Physical Design of the Next Decade

While physical design continues to fight the traditional data capacity and runtime challenges, it has also become critically important to overcome many drawbacks of the silicon technology roadmap.

At the emerging technology nodes, namely 10, 7 and 5 nanometers, sheer complexity hits unprecedented levels. Integration capacity in terms of number of transistors already exceeds 100 billion of transistors per die, with 1 trillion within our reach. Standard-cell complex abutment and multi-VTH design rules pose new placement challenge. Non-planar transistors get smaller and taller, but contacted metal pitch doesn't scale accordingly, thus making pins accessibility harder and introducing new routing congestion issues. Lithography transition to EUV is still unclear, which translates into triple, quadruple, and even octuple patterning cannot be ruled out. Interconnect RC delay not only has by far the lion's share of total delay, but its variation across the stack has reached over one order of magnitude between the lowest (Mx) and the highest (Mz) layers, while the R contribution of vias increases dramatically. Finally, the modelling, characterization, and computing of near-threshold -- ultra-low voltage -- design effects and their impact on timing and power bring design closure up to a much higher level of complexity.

At the established technology nodes, unlike in the past, the oldest nodes are not discontinued. On the contrary, not only the number of active technology nodes in volume production is increasing, but more than 90% of designs in 2016 will be at 45/40 nanometers and above, accounting for more than 60% of wafer production by area. However, today 180 nm designs are radically different from their late 1990s distant relatives. Physical design is increasingly being relied upon to achieve lower area and power, as well as to reduce the required silicon resources in the interest of a better performance and power envelope at a lower cost. Sophisticated physical design methodologies, originally devised for survival at the emerging technology nodes, are more and more frequently used to improve the metrics of the established technology nodes, and to extend their useful lifespan for a very long time.

Production volumes dictate which applications rush to the newest emerging technology nodes and which ones continue to hold at the established nodes. However, it is increasingly difficult to integrate digital computing with analog interfaces, to say nothing about sensors and actuators, energy harvesting or silicon photonics. It is hard to think of digital and true analog & mixed-signal blocks co-existing on the same die at 7 or 5 nanometers. 2.5D-IC and perhaps eventually 3D-IC integration will be required whenever digital computing won't be sufficient.

For all these reasons, the scope of physical design is expanding. On the one hand, all the diverse requirements of a broadening set of technology nodes have to be taken into consideration because our industry cannot afford to develop and maintain different tools for different technology nodes. On the other hand, floorplanners, placers, and routers have to deal with objects and structure beyond the classical digital P&R: as an example, analog placement and routing demand automation that co-exists with interactivity; silicon interposers require "board-level" types of I/O planning and interconnect untangling, along with non-Manhattan routing for re-distribution layers (RDL) among through-silicon vias (TSV) and micro-bumps/pillars. The physical design infrastructure must deal concurrently with multiple dies, implemented using different technology nodes, or for radically different operating conditions.

Physical design in the next decade demands a new wave of innovation to support the needed "revolutionary evolutions", and to continue to deliver the best quality-of-results within acceptable time-to-results.