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Register allocation and instruction scheduling in Unison

Published: 17 March 2016 Publication History

Abstract

This paper describes Unison, a simple, flexible, and potentially optimal software tool that performs register allocation and instruction scheduling in integration using combinatorial optimization. The tool can be used as an alternative or as a complement to traditional approaches, which are fast but complex and suboptimal. Unison is most suitable whenever high-quality code is required and longer compilation times can be tolerated (such as in embedded systems or library releases), or the targeted processors are so irregular that traditional compilers fail to generate satisfactory code.

References

[1]
R. Casta˜neda Lozano. Integrated Register Allocation and Instruction Scheduling with Constraint Programming. Licentiate thesis. KTH Royal Institute of Technology, Sweden, 2014.
[2]
R. Casta˜neda Lozano and C. Schulte. Survey on combinatorial register allocation and instruction scheduling. Technical report, SCALE, KTH Royal Institute of Technology & Swedish Institute of Computer Science, 2014. Archived at arXiv:1409.7628 {cs.PL}.
[3]
R. Casta˜neda Lozano, M. Carlsson, F. Drejhammar, and C. Schulte. Constraint-based register allocation and instruction scheduling. In CP, volume 7514 of LNCS, pages 750–766. Springer, 2012.
[4]
R. Casta˜neda Lozano, M. Carlsson, G. Hjort Blindell, and C. Schulte. Combinatorial spill code optimization and ultimate coalescing. In LCTES, pages 23–32. ACM, 2014.
[5]
C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO, pages 75––88. IEEE, 2004.
[6]
F. M. Q. Pereira and J. Palsberg. Register allocation by puzzle solving. pages 216–226. ACM, 2008.
[7]
Hexagon V4 Programmer’s Reference Manual. Qualcomm, Aug. 2013. Introduction Unison IR Combinatorial Model Status

Cited By

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  • (2024)Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic ProgrammingACM Transactions on Design Automation of Electronic Systems10.1145/364313529:5(1-20)Online publication date: 4-Sep-2024
  • (2021)Generating efficient solvers from constraint modelsProceedings of the 29th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software Engineering10.1145/3468264.3468566(956-967)Online publication date: 20-Aug-2021
  • (2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
  • Show More Cited By

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Published In

cover image ACM Conferences
CC '16: Proceedings of the 25th International Conference on Compiler Construction
March 2016
270 pages
ISBN:9781450342414
DOI:10.1145/2892208
  • General Chair:
  • Ayal Zaks,
  • Program Chair:
  • Manuel Hermenegildo
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 17 March 2016

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Author Tags

  1. combinatorial optimization
  2. instruction scheduling
  3. register allocation

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Cited By

View all
  • (2024)Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic ProgrammingACM Transactions on Design Automation of Electronic Systems10.1145/364313529:5(1-20)Online publication date: 4-Sep-2024
  • (2021)Generating efficient solvers from constraint modelsProceedings of the 29th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software Engineering10.1145/3468264.3468566(956-967)Online publication date: 20-Aug-2021
  • (2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
  • (2017)The Register Allocation and Instruction Scheduling ChallengeProceedings of the 21st Brazilian Symposium on Programming Languages10.1145/3125374.3125380(1-9)Online publication date: 21-Sep-2017
  • (2016)Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.88(30-37)Online publication date: Aug-2016

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