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Comprehensive optimization of scan chain timing during late-stage IC implementation

Published: 05 June 2016 Publication History

Abstract

Scan chain timing is increasingly critical to test time and product cost. However, hold buffer insertions (e.g., due to large clock skew) limit scan timing improvement. Dynamic voltage drop (DVD) during scan shift further degrades scan shift timing, inducing "false failures" in silicon. Hence, new optimizations are needed in late stages of implementation when accurate (skew, DVD) information is available. We propose skew-aware scan ordering to minimize hold buffers, and DVD-aware gating insertion to improve scan shift timing slacks. Our optimizations at the post-CTS and post-routing stages reduce hold buffers by up to 82%, and DVD-induced timing degradation by up to 58%, with negligible area and power overheads.

References

[1]
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch and A. Virazel, "Design of Routing-Constrained Low Power Scan Chains", Proc. DATE, 2004, pp. 62--67.
[2]
A. Cui, T. Yu, G. Qu and M. Li, "An Improved Scan Design for Minimization of Test Power under Routing Constraint", Proc. ISCAS, 2015, pp. 629--632.
[3]
M. Elshoukry, M. Tehranipoor and C. P. Ravikumar, "A Critical-Path-Aware Partial Gating Approach for Test Power Reduction", ACM TODAES 12(2) (2007), pp. 17:1--17:22.
[4]
M. Feuer and C. C. Koo, "Method for Rechaining Shift Register Latches Which Contain More Than One Physical Book", IBM Technical Disclosure Bulletin 25(9) (1983), pp. 4818--4820.
[5]
S. Gerstendörfer and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Journal of Electronic Testing 16(3) (2000), pp. 203--212.
[6]
P. Gupta, A. B. Kahng and S. Mantik, "Routing-Aware Scan Chain Ordering", Proc. ASP-DAC, 2003, pp. 857--862.
[7]
P. Gupta, A. B. Kahng and S. Mantik, "A Proposal for Routing-Based Timing-Driven Scan Chain Ordering", Proc. ISQED, 2003, pp. 339--343.
[8]
M. Hirech, J. Beausang and X. Gu, "A New Approach to Scan Chain Reordering Using Physical Design Information", Proc. ITC, 1998, pp. 348--355.
[9]
L.-C. Hsu and H.-M. Chen, "On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design", Proc. ISQED, 2006, pp. 451--456.
[10]
D. Jayaraman, R. Sethuram and S. Tragoudas, "Gating Internal Nodes to Reduce Power During Scan Shift", Proc. GLSVLSI, 2010, pp. 79--84.
[11]
A. B. Kahng, I. Kang and S. Nath, "Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion", Proc. ICCAD, 2013, pp. 705--712.
[12]
E. L. Lawler, J. K. Lenstra, A. Rinnooy-Kan and D. Shmoys, The Traveling Salesman Problem: A Guided Tour of Combinatorial Optimization, Wiley, 1985.
[13]
J. Lee, S. Narayan, M. Kapralos and M. Tehranipoor, "Layout-Aware, IR-drop Tolerant Transition Fault Pattern Generation", Proc. DATE, 2008, pp. 1172--1177.
[14]
L. Y.-Z. Lin, C. C.-H. Liao and C. H.-P. Wen, "Synthesizing Multiple Scan Chains by Cost-Driven Spectral Ordering", Proc. ASP-DAC, 2013, pp. 540--545.
[15]
M. M. Ozdal, C. Amin, A. Ayupov, S. M. Burns, G. R. Wilke and C. Zhuo, "ISPD-2012 Discrete Cell Sizing Contest and Benchmark Suite", Proc. ISPD, 2012, pp. 161--164, http://archive.sigda.org/ispd/contests/12/ispd2012_contest.html.
[16]
N. Parimi, "Leveraging Physically Aware Design-for-Test to Improve Area, Power, and Timing", https://www.cadence.com/rl/Resources/white_papers/PhysicallyAware_DFT_wp.pdf
[17]
J.-C. Rau, C.-H. Lin and J.-Y. Chang, "An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains", Proc. ATS, 2004, pp. 82--87.
[18]
J. Schulze and R. Tally, "Mitigating Voltage Droop during Scan with Variable Shift Frequency", Proc. ITC, 2014, pp. 1--8.
[19]
S. Seo1, Y. Lee, J. Lee and S. Kang, "A Scan Shifting Method based on Clock Gating of Multiple Groups for Low Power Scan Testing", Proc. ISQED, 2015, pp. 162--166.
[20]
Andres R. Teene, "Clock Skew Insensitive Scan Chain Reordering", US Patent 6539509 B1, May 2003.
[21]
J. T. Tudu, E. Larsson, V. Singh and H. Fujiwara, "Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power", Proc. GLSVLSI, 2010, pp. 73--78.
[22]
W. Zhao, M. Tehranipoor and S. Chakravarty, "Power-Safe Test Application Using An Effective Gating Approach Considering Current Limits", Proc. VTS, 2011, pp. 160--165.
[23]
Hungarian Algorithm, http://www.informatik.uni-freiburg.de/stachnis/index.html
[24]
RedHawk User Guide. https://www.apache-da.com/products/redhawk
[25]
ScanOpt. http://vlsicad.ucsd.edu/GSRC/Bookshelf/Slots/ScanOpt/.
[26]
Synopsys Design Compiler User Guide, http://www.synopsys.com
[27]
Synopsys DFT Compiler User Guide, http://www.synopsys.com
[28]
Synopsys IC Compiler User Guide, http://www.synopsys.com
[29]
Synopsys PrimeTime User Guide, http://www.synopsys.com
  1. Comprehensive optimization of scan chain timing during late-stage IC implementation

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    cover image ACM Other conferences
    DAC '16: Proceedings of the 53rd Annual Design Automation Conference
    June 2016
    1048 pages
    ISBN:9781450342360
    DOI:10.1145/2897937
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 June 2016

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