research-article

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

Authors:

Shaojun WeiAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 64, Pages 1 - 6

https://doi.org/10.1145/2897937.2898001

Published: 05 June 2016 Publication History

Abstract

This paper proposes a context directed pattern matching (CDPM) mechanism, which employs the context of the coarse-grained reconfigurable arrays (CGRAs) as a guide to improve cache prefetching accuracy. CDPM generates a prefetch pattern for an initially executed context, and reuses the pattern to issue prefetch requests when the context is again executed on CGRA. To eliminate the outdated prefetch pattern, CDPM also evaluates the prefetching accuracy of the prefetch pattern at run-time. Experiments showed that CDPM averagely improved performance by 31.1% compared to tests without any prefetching and by 7.7% compared to state-of-the-art prefetching techniques.

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Cited By

Karunaratne MTan CKulkarni AMitra TPeh L(2018)DnestmapProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196027(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196027
Liu LLi ZYang CDeng CYin SWei S(2018)HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs ProcessingIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2017.272881465:3(381-385)Online publication date: Mar-2018
https://doi.org/10.1109/TCSII.2017.2728814
Karunaratne MTan CKulkarni AMitra TPeh L(2018)DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)10.1109/DAC.2018.8465833(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1109/DAC.2018.8465833
Show More Cited By

Index Terms

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Karunaratne MTan CKulkarni AMitra TPeh L(2018)DnestmapProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196027(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196027
Liu LLi ZYang CDeng CYin SWei S(2018)HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs ProcessingIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2017.272881465:3(381-385)Online publication date: Mar-2018
https://doi.org/10.1109/TCSII.2017.2728814
Karunaratne MTan CKulkarni AMitra TPeh L(2018)DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)10.1109/DAC.2018.8465833(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1109/DAC.2018.8465833
Sutter BRaghavan PLambrechts A(2018)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_12(427-472)Online publication date: 14-Oct-2018
https://doi.org/10.1007/978-3-319-91734-4_12
Jung LHochberger C(2018)Lookahead Memory Prefetching for CGRAs Using Partial Loop UnrollingApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_8(93-104)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_8
Yin SYao XLu TLiu DGu JLiu LWei S(2017)Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.268224128:9(2471-2485)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1109/TPDS.2017.2682241

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